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Maximum frequency xillinux

deaxman

Hi, I've heard it said that the maximum frequency that the zedboard can reach is dependant upon the quality of your code.  What does this mean?  If I am using the xillydemo.v file from the xillinux installation, how do I figure out what the maximum frequency is (besides trial and error) and how do I increase this maximum frequency?  Code "quality" is very subjective.  I feel that the maximum would be less dependant on efficiency of your code and more dependant on the number of resources that are being used.  Thanks!

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    Hi,

    There are certain FPGA design practices that help increasing the clock frequency that can be achieved. Most notably, adding pipelining registers (FIFOs) between combinatoric logic elements. The idea is to have as few steps of LUTs and other stuff between each pair of FIFOs, to minimize the settling time (so the next clock can arrive sooner).

    Finding the "maximal" clock is indeed a trial and error thing, with some implementation parameter tweaking coming along. You implement the design, asking for a certain clock in the timing constraints, and see how far you can push it until it fails. How to improve your situation is the subject of a two-day course given by Xilinx: "Designing for Performance".

    To get a general idea of where you stand, you can synthesize a specific module (and its submodules). There is a frequency estimation somewhere at the end of the report. To be taken with a grain of salt, but if often helps.

    Now to xillydemo: This module merely connects you with the Xillybus IP core through FIFOs. In the setting offered in the downloaded bundle, your logic runs on bus_clk, so the FIFOs only take a single clock. It's however common to use FIFOs with two clocks, one for each end (asynchronous FIFOs). If you do this, your logic can use whatever clock you want. So xillydemo isn't really a player here.

    I hope this gave an idea. Getting performance and reliability with proper clocking is what FPGA engineers get (well) paid for. ;)

       Eli

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    Hi,

    There are certain FPGA design practices that help increasing the clock frequency that can be achieved. Most notably, adding pipelining registers (FIFOs) between combinatoric logic elements. The idea is to have as few steps of LUTs and other stuff between each pair of FIFOs, to minimize the settling time (so the next clock can arrive sooner).

    Finding the "maximal" clock is indeed a trial and error thing, with some implementation parameter tweaking coming along. You implement the design, asking for a certain clock in the timing constraints, and see how far you can push it until it fails. How to improve your situation is the subject of a two-day course given by Xilinx: "Designing for Performance".

    To get a general idea of where you stand, you can synthesize a specific module (and its submodules). There is a frequency estimation somewhere at the end of the report. To be taken with a grain of salt, but if often helps.

    Now to xillydemo: This module merely connects you with the Xillybus IP core through FIFOs. In the setting offered in the downloaded bundle, your logic runs on bus_clk, so the FIFOs only take a single clock. It's however common to use FIFOs with two clocks, one for each end (asynchronous FIFOs). If you do this, your logic can use whatever clock you want. So xillydemo isn't really a player here.

    I hope this gave an idea. Getting performance and reliability with proper clocking is what FPGA engineers get (well) paid for. ;)

       Eli

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