Hi all,
I created and added my own IP core "my_ip v1.00.a" to the xillinux EDK project, I can see xillybus_0, xillyvga_0 and my_ip_0 (and of course processing_system7_0).
To be able to access my IP core, I should modify the device-tree, right? Can someone give me a hint?
Thanks in advance.