Background:
I am trying to use the AXI CDMA IP to transfer data from the PL to the DDR memory. I have a Zedboard and I am using the UG873 (V14.2) July 27,2012 user guide as a reference. I am using Version 1.3 and the Zedboard so a couple adjustments in the procedure need to be made to use this user guide. That said, I completed the exercise in Chapter 6 using the standalone application software design. This makes a DMA transfer from one DDR memory location to another. Not sure why you would ever want to that but it does work.
I then added PL to control the LEDs and read the switches and push buttons on the Zedboard. I also added a 32 bit counter to the PL that I will simulate my DMA source with. This counter and the push button switches control the counter value and state. I also added a general input and output port to the processor design that I use to preset some values of the counter and to verify the PL performance. I then modified the standaloane software example to adjust the LEDs and monitor the switches. All these changes were made and passed my testing which include performing the memory to memory example DMA transfer. So far no problem but I have not strayed to far from this and other examples available.
Problem:
Now to do what I really want to do which is DMA transfer from the PL to the DDR memory. I have not seen and could not find an example of this so I have tried to step out on my own.
1.t I changed the DMA source from S_AXI_HP0 slave to an AXI external slave connector. This was recommended in another posting and made sense to me. There are other AXI interface options but I figured a slave port for a slave port would work.
2.tI then assigned an address to the AXI external slave connector to an address out of the DDR memory range. Since this port is external to the processor, I assumed it would need some space of its own. Since the Zedboard DDR memory ends at 0x1ffffff I assigned it to 0x20000000.
3.tSince I am not sure which inputs are need to signal valid data, I made all the input data ports of the AXI external slave connector external connections. I did try just the ones I thought were related to reading from the PL but that did not work either so I selected all of them and set them using the switches on the Zedboard. The only input not connected to the switches is the M_AXI_RDATA which I connected to my counter value.
4.tUsing this setup I did a Design Check without any errors and then successful generated the netlist.
5.tI connected the external ports of the AXI external slave port to my PL logic n PlanAhead . I then generated a bit file successfully.
6.tNow I exported the hardware and bit file and started SDK. I ran the stand alone program and now I get the "XAxiCdma_Interrupt: Failed" message. When I step through the program it gets an error servicing the interrupt. I added print statements before and after the DMA transfer is initiated and there is not change in the memory location where the DMA is supposed to be writing. I have tried adjusting the external inputs with the switches and I get the same error regardless of the input setting
Has anyone successfully made DMA transfers from PL to DDR memory?
What inputs does the DMA slave source need to find the data?
How to configure the DMA controller to look at the AIX external slave connection?
Any suggestions or thoughts would be greatly appreciated.
Thanks
Ted
