EMIO pins

Question

Is there a way to know which EMIO pins are assigned?
Can I get an overview from somewhere?

For example I decide to connect some buttons to GPIO through EMIO.
I want to know the pin number to be able to access from a bare-metal app.

Former Member · Accepted Answer

The Xilinx discrete read convenience function makes the whole thing a little misleading. You shouldn't think in terms of individual pins when it comes to software, you should think in terms of 32-bit registers and specifically the two that comprise the EMIO signals which are available in the PL. The MIO and EMIO pins are both part of the GPIO peripheral. Have a look at UG585, Zynq 700 Technical Reference Manual, section 14. There you will see that there are 4 banks of GPIO. Banks 0 and 1 deal with the MIO signals (note that bank 1 is cut short, there are 22 signals in bank 1 instead of 32 because there are only 54 MIO pins). Bank 2 and bank 3 deal with the 64 EMIO signals. When you fiddle with the EMIO width setting in XPS, that's where you determine how many of the 64 EMIO signals you'll be dealing with. If you choose anything less than 33 for a width, then all of the signals will be in bank 2. If you choose 33 through 64 for a width, then the signals will span both bank 2 and bank 3. The bank 2 signals represent EMIO pin numbers 54 through 85, and the bank 3 signals represent pin numbers 86 through 117. But "pin number" is an artificial construct used by the Xilinx library functions. Have a look at the source code for those functions and you'll see what's going on under the covers is that given a pin number, the bank is calculated, and then the bit within that bank is calculated, the data register for that bank is read in, shifted, and masked to return the single bit represented by the pin number (at least for the discrete read function). A better way to think about the EMIO signals is how they really are, two separate 32-bit registers. After browsing section 14 in UG585, have a look at section B.19 for the details on the various registers involved with the GPIO peripheral (that is to say the MIO and EMIO pins). I found it easier to manipulate the registers of interest directly instead of deciphering the Xilinx convenience functions. But that's just my personal pereference. A summary answer would be the EMIO pin numbers in question will always start at #54 and go up through however wide you decide to make the EMIO port, up to 64 bits. If you go beyond 1 bit wide incidentally, you'll need to specify the GPIO signal name with (0), (1) and so on at the end in the UCF file to LOC each signal to the desired external pin on the Zynq. I hope that helps clear things up a bit for you. Cheers, -Doug

EMIO pins

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