The Zynq TRM states
- All trace lengths must also include the package delay.
- Data Groups should be within +/5ps of DQS
- Addr/Ctrl within +/-10ps of Ck
- Differential pairs should be matched within +/-5 mil
Assuming 160ps/inch for internal FR4 layers, the PCB trace delays are 6.3ps/mm.
ZedBoard Rev C routing does not account for the internal Zynq package delays. Micron DDR3 timing is specified at the package ball, therefore, the DDR3 package delays do not need to be included in the calculations.
Once the Zynq package delays / flight times are incuded in the overall routing delays, the Rev C ZedBoard DDR3 routing violates the recommended guidelines given by Xilinx. However, ZedBoard has gone through extensive testing which shows the memory system works and is stable. The routing skew is just one of many factors that affects the overall performance of the memory system. As shown by ZedBoard, it is possible to violate the skew recommendations and still work, but that is not recommended. For people designing their own Zynq-based platform, it is recommended that you account for the internal Zynq package delay.
The Zynq package delays can be found using an ISE Command prompt with the partgen command. The syntax to obtain the Package file for the ZedBoard Zynq device is:
partgen -v xc7z020clg484
Bryan
