Hi,
I'm trying to design a peripheral to control and collect data from an ADC attached to the PL of the Zynq, I have my design working in simulation but when I synthesise it I end up with lots of constant nets. I also know Vivado is optimising some of the lines on some of the busses away but this is ok as they are not currently used.
The design has BRAM that the PL loads data into from the ADC which is then read by the processor via AXI. I have created a controller on the PL side of the BRAM to allow multiple peripherals to connect to it. This is based around a fifo, that caches instructions to be executed later. Its between this controller and the BRAM that the connection is all 0's, I never get any data out of the BRAM after synthesis.
Anyone with any ideas on what might be wrong?
Thanks
