Hi all,
I have three axi interconnects in my base trd design for the zedboard. AXI_LITE with master and 6 slaves. AXI_HDMI with one DMA where the direction is from memory mapped to streaming. AXI_FILTER with a bidirectional DMA connected to it. AXI_HDMI & AXI_FILTER are connected to AXI high performance ports of the zynq while AXI_LITE is connected to the AXI GP port. PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0 is for AXI_LITE to get an area optimized version.
Strangely, as shown in the attachment, area number for AXI_LITE is significant higher than the other two. This is very counter intuitive. AXI LITE 1 -> 6 architecture should be much simpler than fully connected crossbar for AXI_HDMI and AXI_FILTER.
IPt LUT %LUT FF %FF BRAM %BRAM
AXI_LITE 5156 9% 6855 6% 0 0%
AXI_HDMI 1514 2% 2022 1% 1 0%
AXI_FILTER 3841 7% 5164 4% 5 3%