I have created a project where in the block design there is only one input port, a clocking wizard block and an output port.
The input clock of the clocking wizard (CLK_IN1) is the sysclock.
When the output frequency is higher than 460 MHz there is a timing error after the implementation (TPWS<0) in both cases: PLL and MMCM.
Is it possible to generate a 640 MHz clock with the clocking wizard using as input the 100 MHz sysclock?
Thank you in advance!
