Shared register PS/PL

Hello everyone,

I'm looking for a fast way to transport data (512bit) from the PS to the PL and back. In my project the data arrives at the PS, needs to be processed partly in PS and uses the PL for speeding up the processing. Afterwards the outputdata of the PL needs to be available at the PS. Using RAM would probably be too slow, so I thought of sharing a 32bit register between both. Is this possible? And if so, can anyone give me some advice on how to implement this on the ZedBoard. I'm fairly new to the ZedBoard and the Vivado software.
Thanks in advance,

Dries

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0 Former Member over 10 years ago

Hello Dries,

Interesting question. There are several ways to implement your interface including a shared register interface as you suggest, a dual port BRAM (Block Ram) in the PL or a streaming type interface on one of the Zynq HP ports. In most cases you will probably want to use DMA to speed the transfers. It comes down to the nature of your data (is it streaming like video) and the method you want to use to develop your PL processing design. If you are going to implement the PL processing in hand written HDL code then you may want to use the Vivado 'Create IP' flow which will help you define the interface. If you are planning on defining your PS/PL processing at a higher level of abstraction you may want to investigate the Xilinx SDSoC development environment: http://www.xilinx.com/products/design-tools/software-zone/sdsoc.html

It either case you should probably get a better idea of the basic architecture and capabilities of the Zynq itself before you start. I would suggest looking at the Avnet Zynq SW and HW Speedway workshops to start with:

http://zedboard.org/support/trainings-and-videos

Adam Taylor has a really good blog that goes through developing Zynq design with both the Vivado IP creation and the SDSoC environment:

http://zedboard.org/content/microzed-chronicles

If you are going to stick with the Vivado tool flow Jeff Johnson has some good tutorials as well:

http://www.fpgadeveloper.com/category/tutorials

And if you are a student or educator you may want to take a look at the Xilinx University Program:

http://www.xilinx.com/support/university.html

-Gary
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0 Former Member over 10 years ago

Hello Dries,

Interesting question. There are several ways to implement your interface including a shared register interface as you suggest, a dual port BRAM (Block Ram) in the PL or a streaming type interface on one of the Zynq HP ports. In most cases you will probably want to use DMA to speed the transfers. It comes down to the nature of your data (is it streaming like video) and the method you want to use to develop your PL processing design. If you are going to implement the PL processing in hand written HDL code then you may want to use the Vivado 'Create IP' flow which will help you define the interface. If you are planning on defining your PS/PL processing at a higher level of abstraction you may want to investigate the Xilinx SDSoC development environment: http://www.xilinx.com/products/design-tools/software-zone/sdsoc.html

It either case you should probably get a better idea of the basic architecture and capabilities of the Zynq itself before you start. I would suggest looking at the Avnet Zynq SW and HW Speedway workshops to start with:

http://zedboard.org/support/trainings-and-videos

Adam Taylor has a really good blog that goes through developing Zynq design with both the Vivado IP creation and the SDSoC environment:

http://zedboard.org/content/microzed-chronicles

If you are going to stick with the Vivado tool flow Jeff Johnson has some good tutorials as well:

http://www.fpgadeveloper.com/category/tutorials

And if you are a student or educator you may want to take a look at the Xilinx University Program:

http://www.xilinx.com/support/university.html

-Gary
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