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I've just received a ZedBoard, Use it as a FPGA

Former Member

HI, I want use the Zedboard (use as a FPGA),I'm reading the tutorial for ISE (I didn't use ISE), and this tutorial work on spartan3 , but when I want to create a Digital Clock Manager (DCM) generate the clock:
1. In Project Navigator, select Project > New Source.
2. In the New Source Wizard, select IP (CoreGen & Architecture Wizard)source
3. Click Next.
and in the Select IP dialog box,I select FPGA Features and Design > Clocking, and in this part appear : Clocking Wizard, Spartan3E,Virtex-4,Virtex-5; which I have to chose? or I have to download any library?
image: http://img825.imageshack.us/img825/4610/creatingclock.png
Another thing , I've read in product table :
http://www.xilinx.com/publications/prod_mktg/zynq7000/Zynq-7000-combined...

which say the Z7020 is equivalent to Artix-7 FPGA, that's mean I have to chose IP cores for this kind of FPGA?,
Thanks, and I hope any one can help me

  • 0

    Hi Akael,

    According to UG472, "7 Series FPGAs Clocking Resources":

    7 series devices contain up to 24 CMT tiles. The MMCMs and PLLs serve as frequency synthesizers for a wide range of frequencies, serve as a jitter filters for either external or internal clocks, and deskew clocks.

    The PLL in the 7 series FPGAs, a subset of the MMCM functionality, is based on the MMCM and not necessarily based on previous PLL designs. The additional features supported by the MMCM are:
    u2022 Direct HPC to BUFR or BUFIO using CLKOUT[0:3]
    u2022 Inverted clock outputs (CLKOUT[0:3]B)
    u2022 CLKOUT6
    u2022 CLKOUT4_CASCADE
    u2022 Fractional divide for CLKOUT0_DIVIDE_F
    u2022 Fractional multiply for CLKFBOUT_MULT_F
    u2022 Fine phase shifting
    u2022 Dynamic phase shifting

    I was able to implement a MMCM_ADV device in my design and use it as my clock resource.

    Regards,

    -Kevin

  • 0

    If you select FPGA Features and Design > Clocking > Clocking Wizard, you can get a very simple clock manager
    based upon MMCME2_ADV.  You can use the 100 Mhz input clock, GCLK, that comes in on LOC Y9.  You may need to add GCLK to the .ucf file.

  • 0

    Thank you for your time, I could simulate. Thank you again.