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ZedBoard Hardware Design Different PS DMAC throughput: PL => DDR3, DDR3 => PL
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Different PS DMAC throughput: PL => DDR3, DDR3 => PL

Former Member
Former Member over 12 years ago

Hello,

I configured two different AXI-Slaves which are connected to the GP0 and GP1 port. The AXI clock is 250MHz. The read- and write-acknowledges of AXI are connected to the associated read- and write-chip enables. With the PS DMAC I read some data from the first slave and write it to DDR3 and read some data from DDR3 and write it to the second slave. Both transfers are started successive and I used the same PS DMAC burst size and burst length for both. By writing data to PL the throughput is about 740 MByte /s. The throughput by reading data from PL is about 460 MByte/s.

In ug585 pages 587 to 590 the throughputs of PS DMAC and AXI GP Master Port are the same for reading and writing data.

My question is: Does anyone know why the throughputs are so different between reading and writing data?

Thanks in advance.

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