Hi all,
I created a peripheral with CIP ( AXI4 burst capable high-throughput memory mapped interface), I connected the slave of peripheral to the master GP2 of PS and its Master to the HP0 of PS (64 bits). I choose the option to generate the ISE project and template driver files of peripheral with quite the default options (added software reset). So I keep evrything by default, But when I run the SW application an error appear to me :
*****************************
* User Peripheral Self Test
******************************
User logic slave module test...
- slave register write/read passed
Soft reset test...
- write 0x0000000A to software reset register
- soft reset passed
User logic master module test...
- source buffer address is 0x00102F80
- destination buffer address is 0x00103000
- initialize the source buffer bytes with a pattern
- initialize the destination buffer bytes to zero
- start user logic master module to receive word from the source
- transfer completed
- start user logic master module to send word to the destination
- transfer completed
- destination buffer byte 1 is different from the source buffer
- master module data transfer failed
I try to disable the cache but the same error appear to me.
Any help please???
Mokhtar.
