Hello everybody,
Background: I'm new to the PL world and I'm still trying to figure somethings. I've read some books about VHDL and the design process, however I don't really have practical experience. I'm a computer engineer student and I have a nice experience with software design and some hardware design.
What I'm using:
Zedboard with Xillinux 1.3
Vivado 2014.1
My Objectives:
1st) Understand how the Xillybus works. How I can integrate my logic and see the result at the linux.
2nd) Add some PMODs to the board, retrieve the data from them in the PL, do some processing in the PL and sent the results to the Linux.
As I'm learning, I first want to go around the Xillydemo. My objective here is to design a simple entity (it can be anything, really) and be able to get the result in the Linux host.
I tried to do some modifications in the Xillydemo to sent get the data sent to the fifo_32 and make it appear in the reader of the fifo_8 (only the 8 LSB). However I was unsuccessful (problems in the implementation or no result when testing).
This loopback demo really got me confused I'm stuck into it.
If someone had some demo code or material that I could use to get things going I would very much appreciate it.
I'm looking for something that interacts with the FIFO and I can get the result with the CAT (as in the example), but it's not the loopback. Something that uses the PL to do anything and send the result to the FIFO and to the linux host as consequence.
Hope I'm in the right forum :).
Thank you!