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ZedBoard Hardware Design Make connections to existing IP
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Related

Make connections to existing IP

Former Member
Former Member over 11 years ago

Hello all,

I would like to know the procedure for making connections after adding the existing IP adder /subtraction module.

How do I make connections to the existing IP, especially the adder/subtractor and multiplier modules and how do I communicate with them,  meaning how do I transfer the input store the data, process and get the output and where do I store it. .

Also provide me some additional documentation if any on how do I make those connections.

Thanks and Regards,
Dinesh.

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  • Former Member
    0 Former Member over 11 years ago

    To get a useful answer you will need to be more specific in your question and give some details of your development environment.

     

    What is your host PC operation system (Win 7, Ubuntu, etc.)?

    What version of the Xilinx tools are you using?

    Exactly what IP are you attempting to use. Is this a custom IP or an AXI bus IP in the Vivado catalog or something else?

     

    To answer some of your questions you might want to go through some of the basic tutorial information available here such as the Avnet Zynq Speedway workshops:

    Developing ZynqRegistered-7000 All Programmable SoC Software (Vivado 2013.3)

    Developing ZynqRegistered-7000 All Programmable SoC Hardware (Vivado 2013.3)

    as well as the Zedboard Zynq Concepts Tools and Techniques tutorial: http://zedboard.org/support/design/1521/11

     

    There are also several good blogs out there:

     

    http://zedboard.org/content/zynq-design-scratch

    http://zedboard.org/content/microzed-chronicles-free-e-book-released

    http://www.fpgadeveloper.com/category/tutorials

     

    -Gary

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  • Former Member
    0 Former Member over 11 years ago in reply to Former Member

    I am using a win7 and I am using vivado 2013.4.

    This is not a custom IP created by me.

    This is the adder/substractor, multiplier IP which came with vivado given in the IP catalog.

    Thanks and Regards,
    Dinesh.

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  • Former Member
    0 Former Member over 11 years ago

    The adder/subtractor, as an example, is just a 'logic' block that at it's most basic accepts two 15 bit data inputs, controlled by the 'clk' and 'ce' inputs and provides a 15 bit data output value. How you connect it up depends entirely on what you are trying to accomplish.

     

    As an example, you might want to take a 15 bit data value from an A/D connected to the Programmable Logic portion of the Zynq device to one of the data inputs and set the other 15 bit data input to a constant value. This would require you to define a 15 bit input port and define the device pins connected to each of the 15 bit using a constraints file (.xdc). You would connect 'constant' IP to the other 15 bit data input. You would need to use the clock associated with the A/D to clock the adder/subtractor as well as the CE input. If you wanted to read the output of the block directly by the Zynq ARM Processor you could 'route' 15 bit from the PS GPIO to 'EMIO' and connect them directly to the block outputs.

     

    As to how to make these connections I would suggest you review the tutorial resources referenced above.

     

    -Gary

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  • Former Member
    0 Former Member over 11 years ago

    Hello,

    I have been looking out for some other ways to connect and I figured out that a floating point block.But I was not able to connect the floating point block to the axi interconnect.
    Is there something wrong in my design.

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  • Former Member
    0 Former Member over 11 years ago in reply to Former Member

    The Floating Point IP block has an AXI Streaming interface, which is different than the 'standard' AXI4 interfaces you may be trying to connect to. You can look at some of the Xilinx documentation for details on the axi streaming interface, such as:

     

    UG1037 http://www.xilinx.com/support/documentation/ip_documentation/axi_ref_guide/latest/ug1037-vivado-axi-reference-guide.pdf

     

    and XAPP1168 http://www.xilinx.com/support/documentation/application_notes/xapp1168-axi-ip-integrator.pdf

     

    If you 'google' Zynq axi streaming example you will also find some good videos and other resources.

     

    -Gary

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  • Former Member
    0 Former Member over 11 years ago

    Hi,

    Thank you for your response.

    I have been trying to implement a floating point adder which sends A and B and gets back C.

    We have sent A, B successfully and C is calculated properly which is observed in the logic analyzer.

    I have been using two DMA's for sending A and B and I am getting back C on one of them i.e dma_0.

    For some reason I am not able to get back the calculated value back into C.

    I have also tried the tlast and tlast is getting asserted and the results are shown on the logic analyzer but its not getting back into the C variable and is not printing in the terminal of SDK.

    Could you please help me out with this issue.

    I am using the following
    vivado and sdk- 2013.4 and windows OS.

    Attached is the code.


    #include <stdio.h>
    #include "platform.h"
    #include "ps7_init.h"
    #include <xil_io.h>
    #include "xscugic.h"
    #include "xparameters.h"
    #include "xaxidma.h"

    // AXI DMA Instance
    XAxiDma AxiDma;
    XAxiDma AxiDma1;
    ///////////////////////////////////////initializing DMA 0 //////////////////////////////////////////////////////////////////////////////
    int init_dma(){
    XAxiDma_Config *CfgPtr;
    int status;
    CfgPtr = XAxiDma_LookupConfig(XPAR_AXI_DMA_0_DEVICE_ID);
    if(!CfgPtr){
    print("Error looking for AXI DMA config
    r");
    return XST_FAILURE;
    }
    status = XAxiDma_CfgInitialize(&AxiDma,CfgPtr);
    if(status != XST_SUCCESS){
    print("Error initializing DMA
    r");
    return XST_FAILURE;
    }
    //check for scatter gather mode
    if(XAxiDma_HasSg(&AxiDma)){
    print("Error DMA configured in SG mode
    r");
    return XST_FAILURE;
    }
    /* Disable interrupts, we use polling mode */
    XAxiDma_IntrDisable(&AxiDma,
    XAXIDMA_IRQ_ALL_MASK,XAXIDMA_DEVICE_TO_DMA);
    XAxiDma_IntrDisable(&AxiDma,
    XAXIDMA_IRQ_ALL_MASK,XAXIDMA_DMA_TO_DEVICE);
    return XST_SUCCESS;
    }

    int init_dma1(){
    XAxiDma_Config *CfgPtr;
    int status;
    CfgPtr = XAxiDma_LookupConfig(XPAR_AXI_DMA_1_DEVICE_ID);
    if(!CfgPtr){
    print("Error looking for AXI DMA config
    r");
    return XST_FAILURE;
    }
    status = XAxiDma_CfgInitialize(&AxiDma1,CfgPtr);
    if(status != XST_SUCCESS){
    print("Error initializing DMA
    r");
    return XST_FAILURE;
    }
    //check for scatter gather mode
    if(XAxiDma_HasSg(&AxiDma1)){
    print("Error DMA configured in SG mode
    r");
    return XST_FAILURE;
    }
    /* Disable interrupts, we use polling mode */
    XAxiDma_IntrDisable(&AxiDma1,
    XAXIDMA_IRQ_ALL_MASK,XAXIDMA_DEVICE_TO_DMA);
    XAxiDma_IntrDisable(&AxiDma1,
    XAXIDMA_IRQ_ALL_MASK,XAXIDMA_DMA_TO_DEVICE);
    return XST_SUCCESS;
    }


    int main()
    {
        init_platform();
        ps7_post_config();
        xil_printf("Hello World
    r");
        int status;
        // Init DMA
        status = init_dma();
        if(status != XST_SUCCESS){
        print("rError: DMA init failed
    ");
        return XST_FAILURE;
        }
        print("rDMA0 Init done
    r");

        status = init_dma1();
                if(status != XST_SUCCESS){
                print("rError: DMA init failed
    ");
                return XST_FAILURE;
                }
                print("rDMA1 Init done
    r");


        float A=8.3,B=-3.3,C;
        int whole,thousandths;


        xil_printf("
    raddress of A, B, C is %x,%x",&A,&B);
       //unsigned dma_size=4;
        unsigned int dma_size = sizeof(float);
        //flush the cache

        Xil_DCacheFlushRange((u32) &C,dma_size);

        print("rCache cleared
    r");

        status = XAxiDma_SimpleTransfer(&AxiDma, (u32) &C, dma_size, XAXIDMA_DEVICE_TO_DMA);
        xil_printf("
    rXAxiDMA_SimpleTransfer C status = %d
    ",status);
        if (status != XST_SUCCESS) {
             print("Error RX: DMA transfer from Vivado HLS block failed
    ");
             return XST_FAILURE;
        }

        Xil_DCacheFlushRange((u32) &A,dma_size);
        status = XAxiDma_SimpleTransfer(&AxiDma, (u32) &A, dma_size, XAXIDMA_DMA_TO_DEVICE);
        xil_printf("XAxiDMA_SimpleTransfer A status = %d
    ",status);
        if (status != XST_SUCCESS) {
        print("Error TX: DMA transfer to Vivado HLS block failed
    r");
        return XST_FAILURE;
        }
        print("rTransfer done");
        /* Wait for transfer to be done */
        while (XAxiDma_Busy(&AxiDma, XAXIDMA_DMA_TO_DEVICE)) ;
        print("
    rDMA Finished");


        Xil_DCacheFlushRange((u32) &B,dma_size);
        status = XAxiDma_SimpleTransfer(&AxiDma1, (u32) &B, dma_size, XAXIDMA_DMA_TO_DEVICE);
        xil_printf("XAxiDMA_SimpleTransfer B status = %d
    ",status);
        if (status != XST_SUCCESS) {
        print("Error TX: DMA transfer from Vivado HLS block failed
    ");
        return XST_FAILURE;
        }
        /* Wait for transfer to be done */
        while (XAxiDma_Busy(&AxiDma1, XAXIDMA_DMA_TO_DEVICE)) ;
        print("
    rDMA1 Finished");
    ;
        //poll the DMA engine to verify transfers are complete
        /* Waiting for data processing */

        /* Wait for transfer to be done */
        while ((XAxiDma_Busy(&AxiDma, XAXIDMA_DEVICE_TO_DMA)) ||
        (XAxiDma_Busy(&AxiDma, XAXIDMA_DMA_TO_DEVICE))) ;

        whole=A;
        thousandths=(A - whole) * 100000000;
        xil_printf("
    r This is the value of A in float = %d.%d",whole,thousandths);

        whole=B;
        thousandths=(B - whole) * 100000000;
        xil_printf("
    r This is the value of B in float = %d.%d",whole,thousandths);

        whole=C;
        thousandths=(C - whole) * 100000000;
        xil_printf("
    r This is the value of C in float = %d.%d",whole,thousandths);

        print("
    rEnd of code");
        return 0;
    }

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