Hi all,
If caching and cohrency is disabled on the zynq, does both AXI_HP AND AXI_ACP have similar latency and bandwidth access to the OCM (when both PL and CPU is accessing the OCM)?
Both have similar bandwidths of 1,200 MB/s (Page 541 of Xilinx Zynq TRM).
But it seems the the HP port has to go through two interconnects (Memory and OCM) to access the OCM while ACP only go through the SCU. (Page 118 of Xilinx Zynq TRM). ACP should have a shorter latency access to the OCM.
Is there numbers on this access latency?
Since I want both the ARM and PL to have read/write access to OCM, it seems its better for the PL to have access through HP (even though it may have slower access latency), due to the dual port nature of OCM. Otherwise will there be arbitration latency in the SCU?