PLL Clock isn't working with FSBL

Hi, I work with Xilinx Vivado tools.
I have a design with a custom AXI IP, which receives FCLK_CLK0. When I program the FPGA from the SDK, and run the SW I wrote, everything works great and the clock is running (I'm sensing it via a dedicated port).

On the other hand, if I create a boot image (using a basic FSBL I created with the SDK wizard), and starting up the Zedboard with an SD card, the clock isn't running. I'm guessing the FSBL didn't initiated it, but I can't find out how to solve it.

Needless to say, I asked old Google for a solution, but no avail.

Please help.

Thanks,
David.

0 Former Member over 10 years ago

Make sure that you have added all of the partitions required for your design in the boot.bin you are generating. At a minimum it sounds like you will need your FSBL.elf, a bit file (system_wrapper.bit) and your application .elf file.

There is a good example of how to do this in Tutorial 04 for the MicroZed board found here (same flow should work for the ZedBoard):

http://zedboard.org/support/design/1519/10

If you are still having issues you might try exporting your hardware design to SDK again and 'clean' and 'rebuild' your project.

-Gary
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0 Former Member over 10 years ago

I did it exactly as the tutorial says, and still no clock.
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0 Former Member over 10 years ago

Well, the problem was solved by updating the Vivado software package... Thanks anyway!
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