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Enabling UART0

Former Member

I was wondering if there was any newbie friendly tutorial on enabling UART0, I have very little experience with FPGAs.  I basically need the UART connection as follows:

RX: JE2
TX: JE3

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  • 0

    Hello Jonathan,

    Based on the forum you chose I will assume you are targeting a ZedBoard. I don't know of any tutorials out there addressing this option. If other forum users have seen one please let us know.

     

    On the ZedBoard PMOD pins JE2 and JE3 are directly connected to the Zynq MIO10 and MIO 11 signals already, so no additional location or IO constraints are needed. You can find this information in either the ZedBoard Users Guide or schematic which can be downloaded here:

    http://zedboard.org/support/documentation/1521

     

    Given that the connections are already there it should be pretty easy to add UART 0 to most of the tutorials out there as long as you target the ZedBoard. Once you have your basic Vivado Block Design with your Zynq Processing System IP placed just double click the Zynq block to open up or re-customized the IP. Select "MIO Configuration" from the pane on the left and then expand "I/O Peripherals". There you should be able to check the UART 0 box to enable it. In the drop down box to the right select MIO 10..11". Then click OK to save the changes. Then you should be able to build your hardware design and export to the SDK as you would with most of the tutorials.

     

    Keep in mind that the BSP generated by the SDK will now select UART 0 as the default SDIN and SDOUT ports instead of the UART 1 (USB -UART) port. If you want to continue to use the USB UART as your main terminal port you will need to change the STDIN and STDOUT selections in the BSP back to UART 1.

     

    Also recognize that if you plan to connect the JE2 and JE3 signals to a serial port you will need to use an RS232 signal converter.

     

    -Gary

  • 0 in reply to Former Member

    Hello Gary,
    Thanks for your reply,
    Yes, I am targeting the ZedBoard, I guess I have a few additional questions.  I want to keep UART0 as the default SDIN and SDOUT ports, but I also want to enable UART0.  I guess I don't know how to keep the default SDIN and SDOUT ports as UART0, and also, when I open up the implemented design, do I not need to modify the I/O Std and Site under the I/O ports tab?

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