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Enabling UART0

Former Member

I was wondering if there was any newbie friendly tutorial on enabling UART0, I have very little experience with FPGAs.  I basically need the UART connection as follows:

RX: JE2
TX: JE3

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    Hi Jonathon,

     

    I will assume you mean that you want to add UART0 but keep UART1 as the default SDIN/SDOUT.

     

    You do not need to modify the I/O std or site since the JE PMOD signals are directly connected to an MIO bank that is fixed to 3.3V. Just enable UART0 and select the MIO pins as detailed above. This would not be true if you used one of the PMOD interfaces connected to the Zynq PL pins.

     

    Once you have exported your hardware design to the SDK and generated a BSP you can open up the BSP and change the default SDIN/SDOUT back to UART1 ( the USB-UART connections.

     

    -Gary

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  • 0

    Hi Jonathon,

     

    I will assume you mean that you want to add UART0 but keep UART1 as the default SDIN/SDOUT.

     

    You do not need to modify the I/O std or site since the JE PMOD signals are directly connected to an MIO bank that is fixed to 3.3V. Just enable UART0 and select the MIO pins as detailed above. This would not be true if you used one of the PMOD interfaces connected to the Zynq PL pins.

     

    Once you have exported your hardware design to the SDK and generated a BSP you can open up the BSP and change the default SDIN/SDOUT back to UART1 ( the USB-UART connections.

     

    -Gary

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