Dear community, I am trying to handle up a sensor image in the FPGA. In the past, I just dealt with a differential clock, and used just IBUFGDS without understanding what is going on under the hood. I though I would have to instantiate IBUFG for a single ended clock now, and somehow phase shift the pixel data bus that the sensor is throwing at the FPGA, but I just read the section on IBUFG in UG768 (7series_hdl), which said: "Inference: Recommended", which I didn't know how to interpret.
Procesing a bus data that comes over along with an external clock must be a common task, so I hope I can find an applcation note on this topic. Can anyone please point me in the right direction?
w/ regards,
Henry
