Hi,
I am a newbie to FPGA,
And I have got a Zedboard, when I am trying to implement the XLINX xapper1170 demo (default setting for ZC702) on my Zedboard, I got a platgen error:
Elaborating instances ...
IPNAME:mmult_accel_core_top INSTANCE:mmult_accel_core_top_0 -
C:XILINX14.4ISE_DSPlanAheadexamplesmatrix_mult_crazyproject_1project_1.s
rcssources_1edkmodule_crazymodule_crazy.mhs line 129 - elaborating IP
Generating IP(mmult_accel_core_ap_fadd_2_full_dsp.xco) ...
Failed to generate IP 'mmult_accel_core_ap_fadd_2_full_dsp.xco'!
ERROR:EDK - mmult_accel_core_top_0 (mmult_accel_core_top) -
ERROR:EDK:440 - platgen failed with errors!
Done!
It is kind of strange because the XILINX Chip is the same on both these two boards, and this Pcore was generated in Vivado_HLS using C++ code with choosing only the chip, so I donu00B4t understand why it can not be working?
Can anyone told me how to start with dealing with this problem? Thanks