Hi all,
I am trying to debug the HIL example on the zedboard. Only at the point of calling the AXI transcation (e.g configure_timer(UP_COUNTER, BASE_ADDR_TIMER_1) - WRITE_REG) from the C code, it does a busy waiting. If I step over the line I get remote failure reply error. Also ISIM reports the following errors.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_AWADDR was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_AWVALID was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_AWREADY was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_WDATA was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_WVALID was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_WREADY was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_ARADDR was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_ARVALID was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_S_ARREADY was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_WDATA was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_WVALID was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_WREADY was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_RVALID was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_RREADY was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_RDATA was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_AWADDR was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_AWVALID was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_ARADDR was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_AWREADY was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_ARVALID was not found in the design.
WARNING: Simulation object /testbench/dut/module_1_i/axi_interconnect_1_M_ARREADY was not found in the design.
Though the bitstream(no programming errors as well) and the simulation models compiled properly, it seems the interface that maps the AXI bus from the real hardware to ISM through JTAG tunneling has a bug.How can i debug this?
I also added the following info the hwcosim.bsp file.
'zed-jtag' => {
'Description' => 'ZC702 (JTAG)',
'Vendor' => 'Xilinx',
'Type' => 'jtag',
'Part' => 'xc7z020-1clg484',
'Clock' => [
{
'Period' => 10,
'Pin' => 'Y9',
},
],
'BoundaryScanPosition' => 1,
},
