Hello, everyone. I'm trying to debug a simple IP core with Chipscope(ISE 14.7). This IP core is written in Verilog HDL and connected to PS with AXI Lite. The input clock signal is FCLK2, which is 6.5MHz. After adding an AXI Monitor IP core to the design in XPS, I can successfully monitor the signals of the AXI Lite bus in Chipscope Analyze.
However, no input or output signals of the IP core designed by me can be captured or monitored in Chipscope Analyze, when I adding an ILA IP core to the design in XPS. The input clock signal of ILA is FCLK0, which is 100MHz. In Chipscope Analyze, I import the file "debug_nets.cdc" firstly, but Chipscope cannot display the signals I configure to monitor in XPS. Then I import the file "chipscope_ila_0.cdc". Chipscope displays all the signals normally, but no signals, including FCLK2, can be monitored.(I have tried to trigger single, repeative and unconditional)
After refering to Xilinx Chipscope Tutorial, I also tried to configure ILA in PlanAhead after synthesis process. But the conclusion is the same.
How can I solve this problem? By monitoring AXI bus and debug SDK projects, I am sure that the logic in the PL is in work. Thanks a lot.
