Actions
Forum Thread Details
  • State Not Answered
  • Replies 11 replies
  • Subscribers 353 subscribers
  • Views 2256 views
  • Users 0 members are here
Related

PS SPI Pmod JE7 Hardware system

Former Member

Hello everyone,

I'm in the process of interfacing my Avnet CC3000-Pmod Compatible Wi-Fi Adapter to the ZedBoard via the JE7 Pmod header, which is connected to the PS.

At first I thought this should be a simple thing, since creating a hardware system that includes SPI was so simple, but ...

When I try to use the SPI device (via the SpiPs device driver), I am stuck in the XSpiPs_PolledTransfer() function, waiting for the status register flag that indicates the transmission has finished (XSPIPS_IXR_TXOW_MASK). The reason that the flag never comes, is that I read nonsense values from the register (a 0x2 in this case).
Then I added the XSpiPs_SelfTest() function, which failed at the very first register read. So I'm guessing there is something wrong with my hardware design.

I got the Zynq IP setup & configured as follows:

  +--------------------------------+
  |         ZYNQ               DDR +-----> DDR
  |                       FIXED_IO +-----> FIXED_IO
  |                       USBIND_0 +-
-+ TTC0_CLK0_IN         M_AXI_GP0 +-
-+ TTC0_CLK1_IN    TTC0_WAVE0_OUT +-
-+ TTC0_CLK2_IN    TTC0_WAVE1_OUT +-
+-+ M_AXI_GP0_ACLK  TTC0_WAVE2_OUT +-
| |                      FCLK_CLK0 +--+
| |                  FCLK_RESET0_N +- |
| +--------------------------------+  |
+-------------------------------------+

SPI 1: MIO 10 .. 15
SS[1] IO MIO 14
SPI 1 MIO 10 mosi
SPI 1 MIO 11 miso
SPI 1 MIO 12 sclk
SPI 1 MIO 14 ss[1]

The clock is set to ca. 16MHz, which is the maximum the CC3000 can take.

Has anybody had any experience with the CC3000 Adapter, Pmod or SPI on the ZedBoard? I'd be very glad for any help, since I'm pretty much stuck here.

With best regards,
Darius

Parents
  • 0

    Looking more at the Maxim Pmod implementation, I now note they do not use the MIO or EMIO for anything other than a single UART for communication (over the USB).

    Rather than route the SPI through the MIO or EMIO, it's routed through the General Purpose Master AXI Interface, with the lines defined to have SPI properties.

    Therefore, the MIO on JE doesn't work for the Maxim Pmods, as the Maxim Pmods only work on the PL side, with Pmod connectors JA, JB, JC, and JD. The MIO connected to JE is not used as it's too difficult to reconfigure depending on the module, which is best done with Verilog HDL in the PL logic side.

    The point is that the GP Master AXI Interface may be the best way to configure this SPI interface as well, through one of the Pmods (JA, JB, JC, JD) connected to the PL side.

    Alternatively, defining GP ports on the MIO pins connecting to JE, with software redefinition as suggested by kbarlee, could be another way to go if you're willing to do the line configuratiosn on the software PS side instead of the Verilog PL side.  It could be you only need to reconfigure the IRQ on JE7 in software as the other pins look OK. (Hmmm, are mosi and miso reversed for the PMOD viewpoint?)

    Furthermore, I just now noted the PMOD pin 1 for the CC3000 is ss0 or chip select enable, and connects to PS_MIO13 on the Zynq chip. However, you look to be manipulating PS_MIO14 (or ss[1]) instead of MIO13 (or ss[0]) that's actually connected to the PMOD on pin 1. This is an easy fix, connecting the IRQ is another matter.

Reply
  • 0

    Looking more at the Maxim Pmod implementation, I now note they do not use the MIO or EMIO for anything other than a single UART for communication (over the USB).

    Rather than route the SPI through the MIO or EMIO, it's routed through the General Purpose Master AXI Interface, with the lines defined to have SPI properties.

    Therefore, the MIO on JE doesn't work for the Maxim Pmods, as the Maxim Pmods only work on the PL side, with Pmod connectors JA, JB, JC, and JD. The MIO connected to JE is not used as it's too difficult to reconfigure depending on the module, which is best done with Verilog HDL in the PL logic side.

    The point is that the GP Master AXI Interface may be the best way to configure this SPI interface as well, through one of the Pmods (JA, JB, JC, JD) connected to the PL side.

    Alternatively, defining GP ports on the MIO pins connecting to JE, with software redefinition as suggested by kbarlee, could be another way to go if you're willing to do the line configuratiosn on the software PS side instead of the Verilog PL side.  It could be you only need to reconfigure the IRQ on JE7 in software as the other pins look OK. (Hmmm, are mosi and miso reversed for the PMOD viewpoint?)

    Furthermore, I just now noted the PMOD pin 1 for the CC3000 is ss0 or chip select enable, and connects to PS_MIO13 on the Zynq chip. However, you look to be manipulating PS_MIO14 (or ss[1]) instead of MIO13 (or ss[0]) that's actually connected to the PMOD on pin 1. This is an easy fix, connecting the IRQ is another matter.

Children
No Data