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PS SPI Pmod JE7 Hardware system

Former Member

Hello everyone,

I'm in the process of interfacing my Avnet CC3000-Pmod Compatible Wi-Fi Adapter to the ZedBoard via the JE7 Pmod header, which is connected to the PS.

At first I thought this should be a simple thing, since creating a hardware system that includes SPI was so simple, but ...

When I try to use the SPI device (via the SpiPs device driver), I am stuck in the XSpiPs_PolledTransfer() function, waiting for the status register flag that indicates the transmission has finished (XSPIPS_IXR_TXOW_MASK). The reason that the flag never comes, is that I read nonsense values from the register (a 0x2 in this case).
Then I added the XSpiPs_SelfTest() function, which failed at the very first register read. So I'm guessing there is something wrong with my hardware design.

I got the Zynq IP setup & configured as follows:

  +--------------------------------+
  |         ZYNQ               DDR +-----> DDR
  |                       FIXED_IO +-----> FIXED_IO
  |                       USBIND_0 +-
-+ TTC0_CLK0_IN         M_AXI_GP0 +-
-+ TTC0_CLK1_IN    TTC0_WAVE0_OUT +-
-+ TTC0_CLK2_IN    TTC0_WAVE1_OUT +-
+-+ M_AXI_GP0_ACLK  TTC0_WAVE2_OUT +-
| |                      FCLK_CLK0 +--+
| |                  FCLK_RESET0_N +- |
| +--------------------------------+  |
+-------------------------------------+

SPI 1: MIO 10 .. 15
SS[1] IO MIO 14
SPI 1 MIO 10 mosi
SPI 1 MIO 11 miso
SPI 1 MIO 12 sclk
SPI 1 MIO 14 ss[1]

The clock is set to ca. 16MHz, which is the maximum the CC3000 can take.

Has anybody had any experience with the CC3000 Adapter, Pmod or SPI on the ZedBoard? I'd be very glad for any help, since I'm pretty much stuck here.

With best regards,
Darius

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    Thank you for your helpful replies!

    Hello Kenny,
    Writing my own SPI implementation to work via GPIO would be a practicable solution. Thanks for the input! I will resort to this if I cannot find a different solution.

    Hello Larry,
    I am controlling the CS signal of the CC3000 via GPIO, because of this problem with ss[0]: http://www.xilinx.com/support/answers/47511.htm. I have connected IRQ and PWR_EN the same way and both are working as intended. I can initialize the CC3000 by setting CS and then PWR_EN high and it reacts as intended by pulling IRQ low, which is captured by an GPIO interrupt.

    The real problem is that the registers cannot be read correctly. This manifests in the following symptoms:
    a) The XGpioPs_SelfTest fails at the first register read.
    b) When not performing the SelfTest and transmitting data, the status register reads 0x2, which cannot be right, comes up as all 0s on the memory monitor and the TX fifo empty flag is never set (or read).

    My suspicion is that there is something wrong with the configuration of my hardware system, since my software is almost identical to the Xilinx examples and the problem is something with the registers, as described above. Also the docu of the self test function says it's there to check for errors in the hardware build.

    I'd prefer to connect the Adapter to the PS, not the PL. I'm a bit under time pressure and not yet worked with Xilinx' FPGA tools (except for creating purely PS-based hardware systems).

    Thank you both a lot for your replies!

    Regards,
    Darius

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  • 0

    Thank you for your helpful replies!

    Hello Kenny,
    Writing my own SPI implementation to work via GPIO would be a practicable solution. Thanks for the input! I will resort to this if I cannot find a different solution.

    Hello Larry,
    I am controlling the CS signal of the CC3000 via GPIO, because of this problem with ss[0]: http://www.xilinx.com/support/answers/47511.htm. I have connected IRQ and PWR_EN the same way and both are working as intended. I can initialize the CC3000 by setting CS and then PWR_EN high and it reacts as intended by pulling IRQ low, which is captured by an GPIO interrupt.

    The real problem is that the registers cannot be read correctly. This manifests in the following symptoms:
    a) The XGpioPs_SelfTest fails at the first register read.
    b) When not performing the SelfTest and transmitting data, the status register reads 0x2, which cannot be right, comes up as all 0s on the memory monitor and the TX fifo empty flag is never set (or read).

    My suspicion is that there is something wrong with the configuration of my hardware system, since my software is almost identical to the Xilinx examples and the problem is something with the registers, as described above. Also the docu of the self test function says it's there to check for errors in the hardware build.

    I'd prefer to connect the Adapter to the PS, not the PL. I'm a bit under time pressure and not yet worked with Xilinx' FPGA tools (except for creating purely PS-based hardware systems).

    Thank you both a lot for your replies!

    Regards,
    Darius

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