Actions
Forum Thread Details
  • State Not Answered
  • Replies 11 replies
  • Subscribers 353 subscribers
  • Views 2262 views
  • Users 0 members are here
Related

PS SPI Pmod JE7 Hardware system

Former Member

Hello everyone,

I'm in the process of interfacing my Avnet CC3000-Pmod Compatible Wi-Fi Adapter to the ZedBoard via the JE7 Pmod header, which is connected to the PS.

At first I thought this should be a simple thing, since creating a hardware system that includes SPI was so simple, but ...

When I try to use the SPI device (via the SpiPs device driver), I am stuck in the XSpiPs_PolledTransfer() function, waiting for the status register flag that indicates the transmission has finished (XSPIPS_IXR_TXOW_MASK). The reason that the flag never comes, is that I read nonsense values from the register (a 0x2 in this case).
Then I added the XSpiPs_SelfTest() function, which failed at the very first register read. So I'm guessing there is something wrong with my hardware design.

I got the Zynq IP setup & configured as follows:

  +--------------------------------+
  |         ZYNQ               DDR +-----> DDR
  |                       FIXED_IO +-----> FIXED_IO
  |                       USBIND_0 +-
-+ TTC0_CLK0_IN         M_AXI_GP0 +-
-+ TTC0_CLK1_IN    TTC0_WAVE0_OUT +-
-+ TTC0_CLK2_IN    TTC0_WAVE1_OUT +-
+-+ M_AXI_GP0_ACLK  TTC0_WAVE2_OUT +-
| |                      FCLK_CLK0 +--+
| |                  FCLK_RESET0_N +- |
| +--------------------------------+  |
+-------------------------------------+

SPI 1: MIO 10 .. 15
SS[1] IO MIO 14
SPI 1 MIO 10 mosi
SPI 1 MIO 11 miso
SPI 1 MIO 12 sclk
SPI 1 MIO 14 ss[1]

The clock is set to ca. 16MHz, which is the maximum the CC3000 can take.

Has anybody had any experience with the CC3000 Adapter, Pmod or SPI on the ZedBoard? I'd be very glad for any help, since I'm pretty much stuck here.

With best regards,
Darius

Parents
  • 0

    You are right, Larry. I have not yet bound the ss[0] signal to vcc. This could definitively be the problem! I cannot figure out how to connect it to vcc, though.
    I have routed it to the EMIO, but I don't know where to go from there. Can you give me hint how this is done in Vivado?

  • 0 in reply to Former Member

    Darius,

    The way to connect SS input to VCC is indicated in step 2 of the link you provided. (You already did step 1 in routing to EMIO.) You need to edit the hardware description *.mhs file with a simple text editor. Just double click on it in your project tree. Make a backup before adding the lines below. If you corrupt this file, it won't open your project. (Guess how I know.)

    From http://www.xilinx.com/support/answers/47511.htm :

    When interfacing via MIO or EMIO:

    1. Do not enable the SPI SS0 signal on any of the MIO pins.

    2. Configure the EMIO SPI SS0 port signal in the MHS file so its an output and the SS input is tied to net_vcc:

        PORT processing_system7_0_SPI0_SS_O_pin = processing_system7_0_SPI0_SS_O, DIR = O
        PORT SPI0_SS_O = processing_system7_0_SPI0_SS_O
        PORT SPI0_SS_I = net_vcc

Reply
  • 0 in reply to Former Member

    Darius,

    The way to connect SS input to VCC is indicated in step 2 of the link you provided. (You already did step 1 in routing to EMIO.) You need to edit the hardware description *.mhs file with a simple text editor. Just double click on it in your project tree. Make a backup before adding the lines below. If you corrupt this file, it won't open your project. (Guess how I know.)

    From http://www.xilinx.com/support/answers/47511.htm :

    When interfacing via MIO or EMIO:

    1. Do not enable the SPI SS0 signal on any of the MIO pins.

    2. Configure the EMIO SPI SS0 port signal in the MHS file so its an output and the SS input is tied to net_vcc:

        PORT processing_system7_0_SPI0_SS_O_pin = processing_system7_0_SPI0_SS_O, DIR = O
        PORT SPI0_SS_O = processing_system7_0_SPI0_SS_O
        PORT SPI0_SS_I = net_vcc

Children
  • 0 in reply to Former Member

    Oh, and check to make sure the above example MHS entry is the right syntax name for that SPI0 port as you created in your system.

    Also check that the SS0 input and output are not already defined somewhere else in the MHS file before making a new entry. If so, just edit the existing entry instead.

  • 0 in reply to Former Member

    Thanks for the thorough explanation, but I'm using Vivado 2013.2, which does not have an MHS file in the project directory.

    I found one under C:XilinxVivado2013.2ids_liteISEdatazynqconfigps7_internalsps7_instance.mhs, but it says that it's the "Manually created PS7 Internal peripherals for ps7 instance mhs generation". I can't find any generated mhs files, except in ISE projects, which leads me to the conclusion that Vivado doesn't use MHS files.

    I guess I'll switch back to ISE and report back.

    Thank you very much for all your help, Larry!