Hi
I am trying to make the slave module to control the memory
Of course, I can use IP (like bram controller, or DDR3 controller)
It is for my practice.
As I post the picture, I just want to add my slave modulet (that I already made) with M00_AXI (yellow highlighted). I think I can just match the port between two modules
However, I can't modify any IP.
Can anyone help me out to connect two modules?
is there another way to approach this problem?
or is there any tutorial for this problem?
(like my own PL into system)
ps. I just realized that I can't post any pictures.
my design is based on vivado zynq example by using zynq, axi_interconnet, bram controller (which i want to replace with my own slave module).
If you can help me, i can send you picture by Email.
