About example DMA

Question

Hello every body, I'm studying about dma and follow instruction on http://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html, after generate bitstream. I download file code C named "xaxidma_example_sg_poll.c" on github but I have some questions
1. Why do we have to define MEM_BASE_ADDR is 0x10000000, I read the instruction that we have to configure MEM_BASE_ADDR properly, so what type memory of this address, I have read axiparameter.h and I don't find out which memory of this address.
2. Why do we have to flush cache and invalidate cache, i really confuse about this, is this relative with memory and BD, if we not do this, what'll happen.

Thank you!

Former Member · Accepted Answer

Hello,

Without looking at the code you mention I would assume that it is reserving a block of memory in DDR memory for cache buffers. The DDR memory on the ZedBoard is from address 0x100000 to address x01FF000000.

The cache controller in the ARM CPU is not aware of DMA or other Bus Master memory access to the DDR memory so, if a portion of the memory that you have DMAed to or from is currently cached, then the cache may no longer match the DDR memory. Here are a couple of threads on the Xilinx Community forums that might help:

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Cache-Flushing/td-p/635653

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Zynq-Peripheral-to-Memory-Transfer/td-p/270442

-Gary