Hi,
I designed a simple proof-of-concept IP core, which I want to connect to the Processing System using the EMIO GPIO.
The IP-Core has only two inputs.
A clock input and a reset input.
These two are two different Ports!
I configured the PS EMIO GPIO to be 2-Bit wide.
Now the problem:
I am not able to figure out how to connect the IP-Core to the PSs EMIO GPIO.
It is not possible to "expand" the GPIO Output Vector of the PS.
How do I get the connection right?
I tried to connect both clk and reset to the GPIO_O pin.
After that I looked at the Verilog file of the Block Diagram and found that both, clk and rst where connected to the [0]'s position of the GPIO_O.
It would be easy to modify this file and fix this but unfortunately, this file is read-only!
As a hotfix, I changed the two separate inputs of the IP-Cote to one 2-Bit Vector, but that can't be the solution..
Is there a better way to do this?
Thanks
