PL of zynq

hi
I am currently working on zedboard..I learnt that it has both PS and PL...using vivado we can create a block design..create hdl wrapper, syntheaize, implement and generate bit stream and export to SDK add some drivers and check for output..Incase of using PL ...should we follow the same steps???..Can PL be accessed by just making changes in the ucf or xdc file available???..My need is to use FMC to tranfer some digital data to DAC present at ad-fmcomms1-ebz connnected with zedboard...Is it enough to assign nets in ucf or xdc..or block design should be done and bit stream to be generated????

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0 bhfletcher over 11 years ago
I suggest you start with something simple. Have you already been through the Zynq HW Intro training available at http://zedboard.org/support/trainings-and-videos ?
To give you an idea of the process:

Create IP using HDL or HLS, etc.

Package the IP

Add the IP to the block design

Connect the new IP block to the appropriate interconnect on the PS7

Generate the output products

Edit or regenerate the top-level HDL

Add constraints to XDC

Build, bitstream, export, use SDK, as you suggest above.
This is all covered in the Zynq HW Intro speedway with a simple example.
Bryan
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0 Former Member over 11 years ago in reply to bhfletcher

thank u for ur reply...I have already gone through such design tutorials...Incase of using Virtex-6 we wil write a hdl code...assign some package pins..synthesize..implement..generate bit stream and program FPGA and then check for results...In case of zynq is that not possible to write hdl asper our application assign pins given in and then generating bit stream and then programming FPGA???..
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0 bhfletcher over 11 years ago in reply to Former Member

Yes, you can do that, but it won't be connected to the PS7.
Bryan
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0 bhfletcher over 11 years ago in reply to Former Member

Yes, you can do that, but it won't be connected to the PS7.
Bryan
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