Hello guys~
I am now using bram and bram controller btw PS and PL.
But, due to the restriction of bram, I am considering another way to implement my design.
Recently, I've heard about Virtual FIFO IP using DDR3.
As you know, it is not easy to make system block design through an paper.
Are there anyone who are using Virtual FIFO IP?
Pls let me know how can I make Virtual FIFO based design.
