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Floating Point Implementation

Former Member

I have designed my PID controller in floating point using system generator in SIMULINK.

Could we use the generated code to implement the design on Zynq 7020 FPGA? Or we need to implement it on processing unit (ARM Cortex)?

Thanks.


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    If you need high-speed performance, convert to fixed point, preferably 16 bits, but 24 or 32 if necessary, and target to HDL on the PL. If you need high-accuracy performance, keep it in floating point and target to C code on the PS.

    I designed an FPGA-based PID computation accelerator by adapting arithmetic-intensive portions of a C routine to Verilog. The host processor controlled the base routine and sequencing, passing data to the FPGA for number crunching. The Zynq is designed to do something similar on a single device.

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    If you need high-speed performance, convert to fixed point, preferably 16 bits, but 24 or 32 if necessary, and target to HDL on the PL. If you need high-accuracy performance, keep it in floating point and target to C code on the PS.

    I designed an FPGA-based PID computation accelerator by adapting arithmetic-intensive portions of a C routine to Verilog. The host processor controlled the base routine and sequencing, passing data to the FPGA for number crunching. The Zynq is designed to do something similar on a single device.

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