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AXI GPIO routing

Former Member

I am using Vivado 2014.3.1.
I have a 32 bit wide output-only AXI GPIO port routed to my Verilog top module by instantiation.  I used the IP Integrator to create the AXI GPIO peripheral and made the GPIO port external.  It appears to be functioning as I can send bit values from the PS to turn on or off LEDs that are connected to the PL of the Zedboard.  But, this only works if the registers are written to in the top module.

  If I route the signal from the AXI GPIO port to a different module as follows:

Register the AXI GPIO output from the PS into the top module.->
Place the name of the register attached to the AXI GPIO into the instantiation for the module to which I want to send the signal.

Then no signal reaches the module where the signal is needed.  This is true whether the signal is connected to an LED or my logic->DAC.  No error messages indicate that the registers are trimmed as I have set
(* dont_touch = "true" *) to prevent trimming of these connections.

Creating a wire and using an assign statement between the register that is connected to the AXI GPIO port and the instantiation for the module in which the signal is needed produces a warning indicating that the wire has no driver and that, as a result, the register in the module where I need to use the information has the un-driven pin tied to 0.

Is there a list of rules as to how to route signals originating in the PS that I have missed?

Any suggestions will be appreciated.

Thank you,
Aaron


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    Aaron,

    Hi.  I'm a bit unclear about what you are doing, let me try to recap and see if we can get this straight between us, so we can get you going.

    You are working with a Block Design?

    On the block design page:
    PS AXI Pin ->AXI GPIO -> output (declared as external)
    -or- is it that you are NOT using a Block Design and you just took the AXI-GPIO instantiation code and placed it in your TOP .v file itself?
    I get the feeling that you are using a block design, since you said you declared the pins as external.  Traditionally, when you call out the port map INPUTs and OUTPUTs, the names that match the pin assignments in the .xdc will be assumed as external (since you declared it in the constraint file!)

    Whichever one you chose, this works.

    Then, you took the instantiation code for the AXI GPIO out of the Verilog file and moved it to a file that is declared inside the TOP?

    Did I recap that correctly?

    If you did that, you cannot declare the outputs as external, since they are embedded INSIDE a .v file that is inside of your TOP.  If this is what you did, you will need to do one of two things.
    1. ROUTE the registers FROM the inside .v file to the TOP
    or
    2. route the GPIO from the AXI GPIO block UP to TOP, where you can connect them as external connections (either declaring them in a Block Design, or if you are not using a Block Design, just calling out the proper names in the XDC).

    If you are not using a Block design, is there a reason?  I find it much faster / easier to use this to connect all the logic blocks together and get a good visual about what is connected to what and going where.

    --Dan

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  • 0

    Aaron,

    Hi.  I'm a bit unclear about what you are doing, let me try to recap and see if we can get this straight between us, so we can get you going.

    You are working with a Block Design?

    On the block design page:
    PS AXI Pin ->AXI GPIO -> output (declared as external)
    -or- is it that you are NOT using a Block Design and you just took the AXI-GPIO instantiation code and placed it in your TOP .v file itself?
    I get the feeling that you are using a block design, since you said you declared the pins as external.  Traditionally, when you call out the port map INPUTs and OUTPUTs, the names that match the pin assignments in the .xdc will be assumed as external (since you declared it in the constraint file!)

    Whichever one you chose, this works.

    Then, you took the instantiation code for the AXI GPIO out of the Verilog file and moved it to a file that is declared inside the TOP?

    Did I recap that correctly?

    If you did that, you cannot declare the outputs as external, since they are embedded INSIDE a .v file that is inside of your TOP.  If this is what you did, you will need to do one of two things.
    1. ROUTE the registers FROM the inside .v file to the TOP
    or
    2. route the GPIO from the AXI GPIO block UP to TOP, where you can connect them as external connections (either declaring them in a Block Design, or if you are not using a Block Design, just calling out the proper names in the XDC).

    If you are not using a Block design, is there a reason?  I find it much faster / easier to use this to connect all the logic blocks together and get a good visual about what is connected to what and going where.

    --Dan

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