Hallo,
why the capacitors are used, which does not correspond completely Xilinx recomandation (UG933). For example you are used 10nF, 47nF, 100nF.
What criteria used in the selection of type capacitors?
Thanks
Anton
Hallo,
why the capacitors are used, which does not correspond completely Xilinx recomandation (UG933). For example you are used 10nF, 47nF, 100nF.
What criteria used in the selection of type capacitors?
Thanks
Anton
Anton,
The designers of the Zedboard made their own study, of the power system and its distribution, and chose slightly different components than Xilinx has in its applications notes and users guides.
There is nothing unusual, or wrong, about this. If you do not follow our recommendati0ons, you need to perform sufficient analysis to convince yourself that your solution is at least as good as the one we recommend.
Austin
There is something of a change in bypass capacitor thinking these days. Since the inductance of modern SMT ceramic caps is essentially only dependent on the size (0402, 0603 etc) getting the largest capacitance you can in the smallest size you can is the new rule. So there is a move away from the older staggered value scheme we used to use with leaded parts. There is lots of discussion about this on signal integrity sites and books. Many app notes from suppliers are either fairly old and/or the authors have not quite caught up with the new thinking. Many engineers are not fully into the new way either. Which all goes to show that to some extent bypassing is usually not a decimal-point activity - there is usually quite a bit of leeway to get it "good enough" as long as you are not doing anything silly. But as chips go faster and have more pins and do more stuff, the "good enough" "space" gets smaller and smaller.
Some reading on sites like Howard Johnson's excellent one may be worthwhile:
http://www.sigcon.com/Pubs/pubsKeyword.htm#bypass%20capacitors