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Site location is not valid

reifschneider

Hi,

unfortunateley I have a persistent problem loading a design to my zedboard.

The implementation tool says "[Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid ["C:/rfs/IBDR/ModulesAndIPCores/IntrinsicSecureCryptomodule/HardRSA_ZedBoard/TopModule.xdc":150]".

The Pin is set correctly:

set_property PACKAGE_PIN D11 [get_ports USART_RXD]

and I can assign it properly in the VIVADO pin assignment project.

Subsequently, the following bitstream fails because of missing LOC properties. Only 2 pins are affected, 33 other pins do not cause any trouble.

I tried many things including deleting the synth directories (as proposed in this forum) but nothing helps.

Any idea to get rid of this problem??

Norbert

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    Hi Norbert,

    If you are porting a design from Spartan to Zynq, you are changing the constraint definitions from the older UCF style to XDC. 

    First, XDC is TCL based.  That means that when you are operating on "things" you need to look at them as a set.  My first gut reaction to what you posted is to change it to be:
    set_property PACKAGE_PIN D11 [get_ports {USART_RXD}]
    set_property PACKAGE_PIN C14 [get_ports {USART_TXD}]

    Add the braces where I put them.  You can see examples of this in our Github:
    https://github.com/Avnet/hdl/blob/master/Boards/ZEDBOARD/zedboard_master_XDC_RevC_D_v2.xdc

    Second, I would suggest you look over your constraint file again.  The lines you posted do not look incorrect, however, something elsewhere might be affecting this.  Keep in mind that constraints are loaded in "last" line is used.  That is, the line you posted is very well IN the file, however if that is re-defined elsewhere, later in in your XDC, a bad line will overwrite the line you posted.  Without seeing the entire file, there is not much else I can offer, except that there might be something else causing your issue.

    I will also point out, as Josh mentioned, the forums at Digilent is really where you need to be posting this.
    https://forum.digilentinc.com/

    Lastly, I'll suggest you take a look at some of Xilinx's resources on properly converting UCF to XDC:
    http://www.xilinx.com/video/hardware/migrating-ucf-constraints-to-xdc.html

    --Dan

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  • 0

    Hi Norbert,

    If you are porting a design from Spartan to Zynq, you are changing the constraint definitions from the older UCF style to XDC. 

    First, XDC is TCL based.  That means that when you are operating on "things" you need to look at them as a set.  My first gut reaction to what you posted is to change it to be:
    set_property PACKAGE_PIN D11 [get_ports {USART_RXD}]
    set_property PACKAGE_PIN C14 [get_ports {USART_TXD}]

    Add the braces where I put them.  You can see examples of this in our Github:
    https://github.com/Avnet/hdl/blob/master/Boards/ZEDBOARD/zedboard_master_XDC_RevC_D_v2.xdc

    Second, I would suggest you look over your constraint file again.  The lines you posted do not look incorrect, however, something elsewhere might be affecting this.  Keep in mind that constraints are loaded in "last" line is used.  That is, the line you posted is very well IN the file, however if that is re-defined elsewhere, later in in your XDC, a bad line will overwrite the line you posted.  Without seeing the entire file, there is not much else I can offer, except that there might be something else causing your issue.

    I will also point out, as Josh mentioned, the forums at Digilent is really where you need to be posting this.
    https://forum.digilentinc.com/

    Lastly, I'll suggest you take a look at some of Xilinx's resources on properly converting UCF to XDC:
    http://www.xilinx.com/video/hardware/migrating-ucf-constraints-to-xdc.html

    --Dan

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