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Vivado 2015.3 issue with Zedboard

Former Member

I posted this also on the Xilinx forums, but it looks more related to the board definition file of the Zedboard in Vivado 2015.3


I discovered several unexpected warnings in Vivado when making a basic design with the Zedboard :

just doing these basic steps :

1) create new project, select Zedboard
2) add Zynq
3) run block automation & connection automation
4) connect FCLK_CLK0 to M_AXI_GP0_ACLK
5) create wrapper
6) generate bitstream

In 2014.4 &  2015.2 this worked just fine, howver in 2015.3 :

I get 3 sysnthesis warnings :

[Synth 8-992] S_AXI_GP0_ACLK_temp is already implicitly declared earlier

[Synth 8-992] S_AXI_GP1_ACLK_temp is already implicitly declared earlier

[Synth 8-350] instance 'inst' of module 'processing_system7_v5_5_processing_system7' requires 685 connections, but only 672 given

A placement warning :

[Place 30-12] An IO Bus FIXED_IO_mio with more than one IO standard is found. Components associated with this bus are:

A Route desing warning :

[DRC 23-20] Rule violation (PLIO-7) Placement Constraints Check for IO constraints - An IO Bus FIXED_IO_mio[53:0] with more than one IO standard is found. Components associated with this bus are: LVCMOS18 (FIXED_IO_mio[53], ...

Also, when trying to test a basic LwIP, I get no ethernet communication, so there's definitely something wrong with this

  • 0

    Hello Ronny,

     

    I took a look at your issue by running the same procedure you outline with both Vivado 2015.2 and Vivado 2015.3. As a note I did not see the option for Connection Automation in a basic design with only the Zynq system block, only Block Automation.

     

    The synthesis warnings:

      Synth 8-350] instance 'inst' of module 'processing_system7_v5_5_processing_system7' requires 685 connections, but only 672 given 

     

    and the placement and route warnings:

    A placement warning :

    [Place 30-12] An IO Bus FIXED_IO_mio with more than one IO standard is found. Components associated with this bus are:

    A Route desing warning :

    [DRC 23-20] Rule violation (PLIO-7) Placement Constraints Check for IO constraints - An IO Bus FIXED_IO_mio[53:0] with more than one IO standard is found. Components associated with this bus are: LVCMOS18 (FIXED_IO_mio[53], ...

     

    were both present in Vivado 2015.2 as well. They appear innocuous (even if annoying) and one was discussed in this previous post:

    http://zedboard.org/content/warning-tutorial-01-04-solutions

     

    The other two synthesis warning are new to Vivado 2015.3 but appear harmless as well:

    [Synth 8-992] S_AXI_GP0_ACLK_temp is already implicitly declared earlier

    [Synth 8-992] S_AXI_GP1_ACLK_temp is already implicitly declared earlier

     

    I implemented the designs in both 2015.2 and 2015.3, exported to SDK and  generated the LWIP echo server example application. I downloaded the design via JTAG and both the 2015.2 and the 2015.3 LWIP echo servers seems to work properly for me. Can you verify that there is an issue on your end? I did notice that, when connected to a router, the LWIP echo server did not use the 192.168.1.10 IP address it lists in the LWIP header but one assigned by the router.

     

    We are bringing the issue to Xilinx's attention but you may want to pursue a support case with Xilinx as well. The ZedBoard board definition file is included as part of the Vivado 2015.x tools by Xilinx and not Avnet, so that is a Xilinx issue as well.

     

    -Gary