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Differential connectors JC & JD

anttiw


Can those JC and JD connectors used as single ended input or output?

Or does it need some conversion?

I just need more normal io connections to my Project, not differentials.

BR Antti

  • 0

    Hello Antti,

     

    You can use the ZedBoard JC and JD PMOD signals as single ended inputs or outputs directly, with no conversion.

     

    -Gary

  • 0

    I also have the similar issue of anttiw of using the pmods JC & JD as single ended can you provide any useful link or documentation regarding this issue ?

    Also I need the pmod from PS to be used in PL. Can it be done ?

     

    Regards,

    Omkar

  • 0

    Hellow Omkar,

    While the Zynq signal pins connected to the JC and JD were selected so that differential connections are supported, and the traces are routed as differential signals, you can use each connection as an individual single ended signal. Take a look at the zedboard master XDC user constraints file listed under 'Programmable Logic Master User Constraints' here: http://zedboard.org/support/documentation/1521

    To use this master constraints file just comment out any signals you are not using in your design and substitute the signal names in your design for the default signals listed in the XDC file. As an example, if you wanted to connect a signal in your design, mysignal1, to the PMOD JC pin 1 you would change the following line in the ZedBoard master constraints file:

    # ----------------------------------------------------------------------------
    # JC Pmod - Bank 13
    # ---------------------------------------------------------------------------- 
    set_property PACKAGE_PIN AB6 [get_ports {JC1_N}];  # "JC1_N"
     
    to
     
      # ----------------------------------------------------------------------------
      # JC Pmod - Bank 13
      # ---------------------------------------------------------------------------- 
      set_property PACKAGE_PIN AB6 [get_ports {mysignal1}];  # "description of mysignal1"

    The PL PMODS are all connected to Zynq IO Bank 13, which is fixed to 3.3V VCCIO on the ZedBoard so you will want to leave this line from the master XDC file at the end of your XDC file:

    # Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard. 
    set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
     
    The PS PMOD on the ZedBoard, JE, is directly connected to the Zynq MIO pins and cannot be used with PL signals.
     
    -Gary