SDK Issue : programming FPGA

Hello,

I'm following the steps of the PS configuration lab for the Zedboard.
I did the same block design for my system as the lab's one.
I export the hardware file with bitstream and launch the SDK and there I create a standalone bsp then I create a hello world project. But when launching this on FPGA SDK fails it says :

Failed to download the bitfile
Failed to configure device 2 with bitstream ( ../../.. )
Reason Bitfile is incompatible for this device.

Thank you

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0 Former Member over 9 years ago

Hello,

You don't mention which PS configuration lab you are using. Please post a link.

Also, please tell us what version of the Xilinx tools you are using (and does it match the tools targeted by the lab) and your host PC OS.

It sounds like you targeted a Zynq device that is different than the ZC7020 that is on the ZedBoard. Are you using a ZedBoard?

-Gary
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0 Former Member over 9 years ago

Hello,

You don't mention which PS configuration lab you are using. Please post a link.

Also, please tell us what version of the Xilinx tools you are using (and does it match the tools targeted by the lab) and your host PC OS.

It sounds like you targeted a Zynq device that is different than the ZC7020 that is on the ZedBoard. Are you using a ZedBoard?

-Gary
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0 Former Member over 9 years ago in reply to Former Member

It's the Lab 2 http://zedboard.org/course/developing-zynq%C2%AE-7000-all-programmable-soc-hardware-vivado-20133-and-201441?sid=80616

I'm using xilinx vivado 2014.4.1 on a Virtual machine with CentOS 7.

I did the same configurations as the lab. I'm using a zedboard.
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0 Former Member over 9 years ago in reply to Former Member

Based on the error you received I would guess that may have used the lab instructions for the MicroZed board, which has a 7z7010 device, rather than the ZedBoard lab instructions.

-Gary
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0 Former Member over 9 years ago in reply to Former Member

It was a bug apparently.
I closed the project and re-open Vivado recreate the same design hardware and then export it to the sdk and this time it worked ! I don't know what was the problem but at least I finished the lab.
Now I have an other problem, this time , I have the design and in the SDK I want to create a boot image only frome the FSBL + an elf file and I can't.
What I did is to create a hello application project and then in the option of create zynq boot image I changed the hello.elf by my file.elf. Then , I did program flash and it went fine. but when using Tera Ter ( terminal ) with 115200/8/n/1/n . I have nothing so I guess that what I did is not working. Do you have a solution to how to use an elf file ? There is this xilinx tutorial http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/SDK_Doc/SDK_concepts/concept_faq_debugelfusingsdkwithoutproject.html
But when doing this I cant create a boot image.
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