SDK Issue : programming FPGA

Hello,

I'm following the steps of the PS configuration lab for the Zedboard.
I did the same block design for my system as the lab's one.
I export the hardware file with bitstream and launch the SDK and there I create a standalone bsp then I create a hello world project. But when launching this on FPGA SDK fails it says :

Failed to download the bitfile
Failed to configure device 2 with bitstream ( ../../.. )
Reason Bitfile is incompatible for this device.

Thank you

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0 Former Member over 9 years ago

Not sure exactly what you are trying to implement here. Did you generate the 'my file.elf' with the SDK using the BSP generated for your Zynq hardware design? If not that may be the issue as the my file .elf probably does not match your underlying hardware.

If the my file.ef was generated for your hardware then it looks like a Xilinx tools issue. You might want to post your question on one of the Xilinx Community forums dedicated to tools usage:

https://forums.xilinx.com/

-Gary
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0 Former Member over 9 years ago

Not sure exactly what you are trying to implement here. Did you generate the 'my file.elf' with the SDK using the BSP generated for your Zynq hardware design? If not that may be the issue as the my file .elf probably does not match your underlying hardware.

If the my file.ef was generated for your hardware then it looks like a Xilinx tools issue. You might want to post your question on one of the Xilinx Community forums dedicated to tools usage:

https://forums.xilinx.com/

-Gary
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