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Zedboard read DDR3 from PL

massol

Hi everyone,

I wonder if it's possible to read the DDR3 memory with a custom ip core axi4-lite master interface connected to an interconnect then connected to the HP zynq port ?

Because I'm trying since 3 or 4 weeks to do that and that's give me wrong things.

(I use an ILA to see what's happen on the master/slave communication.)

I write DDR3 in SDK via ps : Xil_Out32(DDR_BASE_ADDRESS, 0x00000001); so at the 0x10000000 ddr3 address, write 0x00000001 data.

Then I want to read this data via my PL custom ip(this ip is just a redirection): Xil_Out32(MY_IP_BASE_ADDRESS, DDR_BASE_ADDRESS); so I send to my ip the address to read.

And then I read my ip register which normally store the data : data = Xil_In32(MY_IP_BASE_ADDRESS + REGISTER_1); so read address 0x43C00004 and the data is not 0x00000001 but 0x9FA90DDC (On the ILA) and 0x9FA90DDD on the sdk terminal;


Someone can help me to understand ?

I use Vivado 2013.4 on windows 7 machine.

Thanks for your help,

Best regards.

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  • 0

    For people that go crazy about "solved" problems without ACTUAL SOLUTIONS, here is one if my experiments:

    - either disable caches for good

    - or flush the cache before reading the data


    This is what an SDK hello application looks like then:

    #include <stdio.h>
    #include "platform.h"
    #include <unistd.h>

    #include "xparameters.h"
    #include "xil_io.h"
    #include "xstatus.h"
    #include "xscugic.h"
    #include "xil_exception.h"

    #include "ps7_init.h"
    #include "xil_cache.h"

    #define PARAM_BASE_ADDRESS               0x00000000

    int main()
    {
    t// initialization
        init_platform();
        //ps7_init();
        ps7_post_config();
        // cleanup_platform();ttttttttt// DISABLING CACHES


        // variables
        u32 offset;
        u32 param;
        int i = 0;
        xil_printf(" PL WRITING & PS READING DRAM MEMORY TEST ");

        // loop
        while ( 1 ) {

        tgetchar();

        tXil_DCacheFlushRange(PARAM_BASE_ADDRESS, 4*1);      // CACHE FLUSHING
        toffset = 0X00000000;
        tfor (i = 0; i < 50 ; i++){ttttttt// LOOP FOR READING DATA
        ttparam = Xil_In32(PARAM_BASE_ADDRESS + offset);
            txil_printf("mem_read %d : %x
    r",i , param);
            toffset = offset + 4;
        t}
        }

        cleanup_platform();
        return 0;
    }

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  • 0

    For people that go crazy about "solved" problems without ACTUAL SOLUTIONS, here is one if my experiments:

    - either disable caches for good

    - or flush the cache before reading the data


    This is what an SDK hello application looks like then:

    #include <stdio.h>
    #include "platform.h"
    #include <unistd.h>

    #include "xparameters.h"
    #include "xil_io.h"
    #include "xstatus.h"
    #include "xscugic.h"
    #include "xil_exception.h"

    #include "ps7_init.h"
    #include "xil_cache.h"

    #define PARAM_BASE_ADDRESS               0x00000000

    int main()
    {
    t// initialization
        init_platform();
        //ps7_init();
        ps7_post_config();
        // cleanup_platform();ttttttttt// DISABLING CACHES


        // variables
        u32 offset;
        u32 param;
        int i = 0;
        xil_printf(" PL WRITING & PS READING DRAM MEMORY TEST ");

        // loop
        while ( 1 ) {

        tgetchar();

        tXil_DCacheFlushRange(PARAM_BASE_ADDRESS, 4*1);      // CACHE FLUSHING
        toffset = 0X00000000;
        tfor (i = 0; i < 50 ; i++){ttttttt// LOOP FOR READING DATA
        ttparam = Xil_In32(PARAM_BASE_ADDRESS + offset);
            txil_printf("mem_read %d : %x
    r",i , param);
            toffset = offset + 4;
        t}
        }

        cleanup_platform();
        return 0;
    }

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