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ZedBoard Hardware Design LWIP-ECHO SERVER NOT WORKING
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Related

LWIP-ECHO SERVER NOT WORKING

Former Member
Former Member over 9 years ago

Hi everyone,

I am trying to design a PL ethernet for my motor controller unit connected to the fmc. I created the design, mapped the ethernet to appropriate pins, generated the bitstream and exported the bitstream to the sdk.

In the sdk I selected lwip, after that I directlty programmed fpga and ran the code. But the echo server is not working. Its shown like

-----lwIP TCP echo server ------
TCP packets sent to port 6001 will be echoed back
auto-negotiated link speed: 69073

After that nothing. I am pretty sure thatI have written the constraints correctly. I am attaching the block diagram tcl file and the hdf files along with this. What am I missing? Please enlighten me. Thanks in advance.

I am using Zedboard and I am using the ethernet port from the motor controler. I dont think there is any problem with the design. Please help me out here.

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  • Former Member
    Former Member over 9 years ago +1 verified
    Hi Thanks for the reply. I just found out the problem with the design. I was using a timer and interrupt controller and connected the intr pin of the intc to the concat along with the interrupts from dma…
  • Former Member
    0 Former Member over 9 years ago

    Hello Karthik,

     

    First, please do not post the same question to multiple forums http://zedboard.org/content/lwip-echo-server-not-working.

     

    You will not be able to attach your design files and without that information we do not really know enough to get started. Are you using the second PS Ethernet controller and routing the signals to the PL via EMIO or implementing a 'soft' PL based Ethernet MAC? If so which Ethernet IP are you using.

     

    What external PHY are you using and what bus (MII, GMII or RGMII) are you implementing to connect? How are you controlling the MDIO interface?

     

    Can you tell us what motor control FMC card you are using? Is there an example or reference design for that board you are following?

    What version of the Xilinx tools are you using?

    What is your host OS, Linux or Windows?

     

    -Gary

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  • Former Member
    0 Former Member over 9 years ago in reply to Former Member

    First of all sorry for posting the same question in two forums. I was confused whether to post it in hardware or software forums.
    Thanks for the response Gary.
    We are using AXI Ethernet in our design and we are mapping it to the fmc to which we are connecting my motor controller. The motor controller we are using is AD-FMCMOTCON1-EBZ. The PHY we are using is 88E1512 Marvell Integrated 10/100/1000 Mbps Energy Efficient Ethernet Transceiver. I am really confused here. Please help me out.
    There is no example design for the board we are using.
    So I am using
    https://github.com/fpgadeveloper/zedboard-qgige
    as reference. Iam working in windows.
    Vivado 2015.4
    sdk 2015.4
    Waiting for your reply. Thanks in advance.

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  • Former Member
    0 Former Member over 9 years ago in reply to Former Member

    Hi Gary,
            This is the design.
    https://xlnx.i.lithium.com/t5/image/serverpage/image-id/25162i3202B85153CA0B53/image-size/original?v=mpbl-1&px=-1
    Is there any problem in the design? Is the timer and interrupt controller connected properly??
    Please help me in this.
    Thanks
    Karthik R

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  • mbrown
    0 mbrown over 9 years ago

    Hello Karthik,

     

    You might find some guidance in studying the ADI reference design for AD-FMCMOTCON1-EBZ.

    https://wiki.analog.com/resources/eval/user-guides/ad-fmcmotcon2-ebz/reference_hdl

    source code -- https://github.com/analogdevicesinc/hdl/tree/hdl_2015_r2/projects

     

    It anables 2x Ethernet ports entering Zynq through the PL.

     

    /Matt

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  • Former Member
    0 Former Member over 9 years ago in reply to mbrown

    Hi Matt,
           Thanks for sharing this design, but lets leave the fact that I am using a motor controller. I am using an axi ethernet ip through which I need to communicate with the ethernet port in the device connected to the fmc port of the zedboard.I have shared the design in my previous comment. I have mapped it correctly too. Even then I cannot communicate with the ethernet port. Pleae enlighten me here.
    Thanks
    Karthik R

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  • Former Member
    0 Former Member over 9 years ago

    Hi
    Thanks for the reply. I just found out the problem with the design. I was using a timer and interrupt controller and connected the intr pin of the intc to the concat along with the interrupts from dma and temac. I removed the timer and intc, now its working fine.
    Thanks for the reply
    Karthik R

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  • adithyakrish
    0 adithyakrish over 8 years ago

    Hello Karthik R,

    I aḿ a student who is now learning Vivado. I ttred the design you mentioned earlier but the Bitstream is not getting generated. Then, I followed the correction (The very last post) and I removed the Interrupt Controller and Timer from the design. But now the could not even create a wrapper because the output of the concat is not connected anywhere.

    Can you please share the corrected design?

    Or could you please help me with the problem? 

    Eagerly waiting for the reply,

    Thanks,

    Adithya Krish

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  • Former Member
    0 Former Member over 8 years ago in reply to adithyakrish

    Hi Adithya Krish
    I don't have that design right now. But if you share the picture of the block and the error I might be able to help you.
    Thanks
    Karthik

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  • adithyakrish
    0 adithyakrish over 8 years ago

    imageHello, 

    Thank you for the swift reply.

    I am new to Vivado and the design is more or less the same as you posted above in your previous comment.

    The problem is as follows,

    1) I designed the above system and saw your solution and did as per the solution.

    2) but once I removed AXI INTC and AXI Timer, the output of the concat which was previously given as input to the the timer was left  to standalone. I did not know  how to proceed then on.

    3) I tried the above design and what the error was 

    [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
    design_1_i/axi_ethernet_0/U0/eth_mac/U0/tri_mode_ethernet_mac_i/bd_0_eth_mac_0_core (tri_mode_ethernet_mac_v9_0)
     
    Please help me as soon as possible. 
     
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  • adithyakrish
    0 adithyakrish over 8 years ago

    image

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