I design an embedded system which uses PS to control 8 leds. I add AXI General Purpose IO into PL. I connect PS to PL with GP ports.
I modify the UCF with the code like:
NET LD[0] LOC = T22 | IOSTANDARD = LVCMOS33;
NET LD[1] LOC = T21 | IOSTANDARD = LVCMOS33;
NET LD[2] LOC = U22 | IOSTANDARD = LVCMOS33;
NET LD[3] LOC = U21 | IOSTANDARD = LVCMOS33;
NET LD[4] LOC = V22 | IOSTANDARD = LVCMOS33;
NET LD[5] LOC = W22 | IOSTANDARD = LVCMOS33;
NET LD[6] LOC = U19 | IOSTANDARD = LVCMOS33;
NET LD[7] LOC = U14 | IOSTANDARD = LVCMOS33;
But when I generate bitstream, error appears:
ERROR:Bitgen:342 - This design contains pins which have locations (LOC) that are
not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned.
This may cause I/O contention or incompatibility with the board power or
connectivity affecting performance, signal integrity or in extreme cases
cause damage to the device or the components to which it is connected. To
prevent this error, it is highly suggested to specify all pin locations and
I/O standards to avoid potential contention or conflicts and allow proper
bitstream creation. To demote this error to a warning and allow bitstream
creation with unspecified I/O location or standards, you may apply the
following bitgen switch: -g UnconstrainedPins:Allow
This message applies to the following I/O ports:
axi_LDs_GPIO_IO_pin<0>
axi_LDs_GPIO_IO_pin<1>
axi_LDs_GPIO_IO_pin<2>
axi_LDs_GPIO_IO_pin<3>
axi_LDs_GPIO_IO_pin<4>
axi_LDs_GPIO_IO_pin<5>
axi_LDs_GPIO_IO_pin<6>
axi_LDs_GPIO_IO_pin<7>
What's the problem? How to solve it?
