DDR3 Power up - Initialization sequence

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DDR3 Power up u2013 Initialization sequence

BACKGROUND:
To Power up the DDR3 on the Zedboard, an initialization sequence is required. (See link below for general informations).
https://deakons.fedorapeople.org/tn4107_power_up_initialization_and_reset.pdf
In this sequence are different memory configuration possible, by sending MRS commands to the DDR3 memory. I want to understand how the Power up sequence works, and how can I adjust the MRS commands. So maybe someone can help me with this questions.

QUESTION:
u2022tWhere do I have to send these DDR3 MRS commands? (i.e in the Bootloader)
u2022tIs there a special method to Init the DDR3 Memory, or where is the initialization be done?
u2022tAre there any documentations regarding the DDR3 Power up initialization (i.e. Technical References, or maybe programming files or something else)?

Thanks for your help!!!!

0 zedhed over 10 years ago

Hi hb_zed,

The Zynq First Stage Boot Loader (FSBL) is responsible for DDR3 memory initialization prior to loading the first user application. The memory configuration is inherited from the hardware project developed within Vivado Design Suite. When the hardware platform is exported to SDK, the ps7_init.h and ps7_init.c files are generated. This code contains the register initialization information that the FSBL uses to initialize all of the Zynq hardware (including the DDR controller).

You can take a look at Xilinx UG585 which may give you some insight into the DDR3 initialization process from the Zynq perspective.

http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

Regards,

-Kevin
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