Hi there,
I've been working on a project where I have had to implement a custom MAC (basically a heavily modified version of the ethernet tri mac from OpenCores.org).
The design in XPS passes DRC and generates a netlist with no errors but when it comes to generating a bitstream, I get the errors, shown below, on the 4 transmit pins and clock.
I have disabled the internal Eth0 device and added the specific RGMII pins to system.ucf as shown below the error log.
I have made these ports external in XPS and connected the Xilinx gmii_to_rgmii(v1.00.a) adapters RGMII interface to those pins and then connected the GMII interface to the custom MAC.
Does anyone know what I might need to do to configure the pins correctly? Is there a setting I'm missing somewhere?
Please forgive the messy text, there doesn't seem to be a <code> tag on this forum that I'm aware of.
------------------------- Start of Error Log -------------------------
ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
single IOB component because the site type selected is not compatible.
Further explanation:
The component type is determined by the types of logic and the properties and
configuration of the logic it contains. In this case an IO component of type
IOB was chosen because the IO contains symbols and/or properties consistent
with input, output, or bi-directional usage and contains no other symbols or
properties that require a more specific IO component type. Please double
check that the types of logic elements and all of their relevant properties
and configuration options are compatible with the physical site type of the
constraint.
Summary:
Symbols involved:
tBUF symbol "ETH_RGMII_TXD_0_OBUF" (Output Signal = ETH_RGMII_TXD<0>)
tPAD symbol "ETH_RGMII_TXD<0>" (Pad Signal = ETH_RGMII_TXD<0>)
Component type involved: IOB
Site Location involved: E9
Site Type involved: IOPAD
------------------------- End of Error Log -------------------------
------------------- Start of System.ucf additions --------------------
net ETH_RGMII_RXD<0> tLOC = E11 | IOSTANDARD = LVCMOS18;
net ETH_RGMII_RXD<1> tLOC = B7 | IOSTANDARD = LVCMOS18;
net ETH_RGMII_RXD<2> tLOC = F12 | IOSTANDARD = LVCMOS18;
net ETH_RGMII_RXD<3> tLOC = A13 | IOSTANDARD = LVCMOS18;
net ETH_RGMII_RX_CTRLtLOC = D7 | IOSTANDARD = LVCMOS18;
net ETH_RGMII_RX_CLKtLOC = A14 | IOSTANDARD = LVCMOS18;
net ETH_RGMII_TXD<0> tLOC = E9 | IOSTANDARD = LVCMOS18;
net ETH_RGMII_TXD<1> tLOC = A7 | IOSTANDARD = LVCMOS18;
net ETH_RGMII_TXD<2> tLOC = E10 | IOSTANDARD = LVCMOS18;
net ETH_RGMII_TXD<3> tLOC = A8 | IOSTANDARD = LVCMOS18;
net ETH_RGMII_TX_CTRL LOC = F11 | IOSTANDARD = LVCMOS18;
net ETH_RGMII_TX_CLK LOC = D6 | IOSTANDARD = LVCMOS18;
net ETH_RGMII_MDIO LOC = C12 | IOSTANDARD = LVCMOS18;
net ETH_RGMII_MDC LOC = D10 | IOSTANDARD = LVCMOS18;
------------------- End of System.ucf additions ----------------------
