Hello,
I am trying to apply simple example on ZED Board for partial reconfiguration. I synthesis my vhdl code in XILINX ISE and used to NGC file of the top entity in the PlanAhead but the modules didn't appear in the Synthesized Design here is my vhdl code :
entity TopEntity is
Port ( Switch : in STD_LOGIC_VECTOR (7 downto 0);
LED : out STD_LOGIC_VECTOR (7 downto 0));
end TopEntity;
architecture Behavor of TopEntity is
component SwitchLedController is
Port ( Switch : in STD_LOGIC_VECTOR (7 downto 0);
LED : out STD_LOGIC_VECTOR (7 downto 0));
end component;
begin
partial: SwitchLedController port map(Switch, LED);
end Behavor;
