Hello everybody
I am using vivado logic analyzer to debug the output from my hls design. How can i configure the analyzer to capture the data when multiple interrupts occur?
Thanks
Hello everybody
I am using vivado logic analyzer to debug the output from my hls design. How can i configure the analyzer to capture the data when multiple interrupts occur?
Thanks
Hello Fotis,
We go over using the VIvado Logic Analyzer in the Developing Zynq Hardware Speedway. To do this we use the ILA Logic core. Please refer to the Developing Zynq Hardware Speedway located here. Specifically refer to Lab 8.
--Josh
Hello Fotis,
We go over using the VIvado Logic Analyzer in the Developing Zynq Hardware Speedway. To do this we use the ILA Logic core. Please refer to the Developing Zynq Hardware Speedway located here. Specifically refer to Lab 8.
--Josh