I'm new user of ZEDboard and my question might be a beginner question. I' sorry for that.
On the first hardware implementation of my system, I have established a communication channel between the PS-PL. For that I have used AXI GPIO vivado IP.
The AXI GPIO block has a bit width of 62 bits divided into two channels of 32 bits (GPIO and GPIO2). the base register address of the AXI GPIO was 0x4126_0000 (64k range). Thus, the higher address corresponds to 0x4126_FFFF.
I access the fisrt channel, the 32 lsb (GPIO) using the register address 0x4126_0000 and the second channel, the 32 msb (GPIO2) using the register address 0x4126_0008.
In such way the hardware implementation of my system was working fine.
The issue is the following:
Now 64 bit width is not sufficient for my second HW implementation of the system. I must transfer between PS-PL at least 90 bits.
So far the unique solution i have found, was to use an additional AXI GPIO block for the additional bits. This new AXI GPIO block has base address 0x4127_0000 and high address 0x4127_FFFF (64k range).
1st QUESTION
Is there any way to use for the second AXI GPIO IP addresses within the range of my first AXI GPIO IP. For instance access the first channel of my second AXIO GPIO using the register address 0x4126_0010 instead of 0x4127_0000?!
2nd QUESTION
Is there any vivado IP which implements the AXI GPIO functionality but with a bit width larger than 62 bits? Something that looks like and AXI GPIO but with 3 Channels or more rather than 2 (GPIO GPIO2).
Thank you very much
