1. I have used the design of zedboard XAPP1079 in which two baremetal application are run on two different cpu of zedboard.
2. Using that design i want to write data using CPU0 on ON-CHIP-MEMORY and read the same data using cpu1 From ON-CHIP-MEMORY. The code for the same is provided below.
3. Writing the data is done perfectly but while reading some garbage values are read as shown below.
4. Can anyone help on these?
CPU0:
#include <stdio.h>
#include "xil_io.h"
#include "xil_mmu.h"
#include "xil_exception.h"
#include "xpseudo_asm.h"
#include "xscugic.h"
#include "sleep.h"
#define INTCtt XScuGic
#define INTC_DEVICE_IDtXPAR_PS7_SCUGIC_0_DEVICE_ID
#define INTC_HANDLERtXScuGic_InterruptHandler
#define sev() __asm__("sev")
#define CPU1STARTADR 0xfffffff0
#define COMM_VAL (*(volatile unsigned long *)(0xFFFF0000))
static int SetupIntrSystem(INTC *IntcInstancePtr);
INTC IntcInstancePtr;
int main()
{
tint Status;
txil_printf("cpu0
");
//Disable cache on OCM
Xil_SetTlbAttributes(0xFFFF0000,0x14de2); // S=b1 TEX=b100 AP=b11, Domain=b1111, C=b0, B=b0
COMM_VAL = 0;
/////////////////////////////////////
u32ti,j=0;
u32thigh_addr=0x0020ffff;
u32 readvalue,value=0,valuer=0;
// init_platform();
print("Hello World
r");
xil_printf("High address=%d
", high_addr);
tttfor(i=0x0020ff00;i<high_addr;i++)
ttt{
tttif(value==65537)
ttttvalue=0;
ttttXil_Out16(XPAR_DDR_MEM_BASEADDR+(2*i),value);
tttxil_printf("value at address is %d
",value);
tttvalue++;
}
/////////////////////////////////////
t// Initialize the SCU Interrupt Distributer (ICD)
tStatus = SetupIntrSystem(&IntcInstancePtr);
tif (Status != XST_SUCCESS) {
ttreturn XST_FAILURE;
t}
print("CPU0: writing startaddress for cpu1
r");
Xil_Out32(CPU1STARTADR, 0x00200000);
dmb(); //waits until write has finished
print("CPU0: sending the SEV to wake up CPU1
r");
sev();
while(1){
tsleep(5);
ttprint("CPU0: Hello World CPU 0
r");
ttsleep(5);
ttCOMM_VAL = 1;
ttwhile(COMM_VAL == 1);
}
return 0;
}
static int SetupIntrSystem(INTC *IntcInstancePtr)
{
tint Status;
tXScuGic_Config *IntcConfig;
t/*
t * Initialize the interrupt controller driver so that it is ready to
t * use.
t */
tIntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
tif (NULL == IntcConfig) {
ttreturn XST_FAILURE;
t}
tStatus = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
tttttIntcConfig->CpuBaseAddress);
tif (Status != XST_SUCCESS) {
ttreturn XST_FAILURE;
t}
t/*
t * Initialize the exception table
t */
tXil_ExceptionInit();
t/*
t * Register the interrupt controller handler with the exception table
t */
tXil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
ttt (Xil_ExceptionHandler)INTC_HANDLER,
ttt IntcInstancePtr);
t/*
t * Enable non-critical exceptions
t */
tXil_ExceptionEnable();
treturn XST_SUCCESS;
}
CPU1:
#include "xparameters.h"
#include <stdio.h>
#include "xil_io.h"
#include "xil_mmu.h"
#include "xil_cache.h"
#include "xil_exception.h"
#include "xscugic.h"
#include "sleep.h"
#define INTCtt XScuGic
#define INTC_HANDLERtXScuGic_InterruptHandler
#define INTC_DEVICE_IDtXPAR_PS7_SCUGIC_0_DEVICE_ID
#define PL_IRQ_ID XPS_IRQ_INT_ID
#define IRQ_PCORE_GEN_BASE XPAR_IRQ_GEN_0_BASEADDR
#define COMM_VAL (*(volatile unsigned long *)(0xFFFF0000))
/**
* This typedef contains configuration information for the device driver.
*/
typedef struct {
tu16 DeviceId;tt/**< Unique ID of device */
tu32 BaseAddress;t/**< Base address of the device */
} Pl_Config;
/**
* The driver instance data. The user is required to allocate a
* variable of this type.
* A pointer to a variable of this type is then passed to the driver API
* functions.
*/
typedef struct {
tPl_Config Config; /**< Hardware Configuration */
tu32 IsReady;tt/**< Device is initialized and ready */
tu32 IsStarted;tt/**< Device is running */
} XPlIrq;
void Xil_L1DCacheFlush(void);
static int SetupIntrSystem(INTC *IntcInstancePtr, XPlIrq *PeriphInstancePtr, u16 IntrId);
static void DisableIntrSystem(INTC *IntcInstancePtr, u16 IntrId);
static void PlIntrHandler(void *CallBackRef);
extern u32 MMUTable;
/**
* Assign the driver structures for the interrupt controller and
* PL Core interrupt source
*/
INTC IntcInstancePtr;
XPlIrq PlIrqInstancePtr;
// Global for IRQ communication to main()
int irq_count;
int main()
{
tint Status;
xil_printf("cpu1
");
//Disable cache on OCM
tXil_SetTlbAttributes(0xFFFF0000,0x14de2); // S=b1 TEX=b100 AP=b11, Domain=b1111, C=b0, B=b0
print("CPU1: init_platform
r");
irq_count = 0;
// Initialize driver instance for PL IRQ
PlIrqInstancePtr.Config.DeviceId = PL_IRQ_ID;
// PlIrqInstancePtr.Config.BaseAddress = IRQ_PCORE_GEN_BASE;
PlIrqInstancePtr.IsReady = XIL_COMPONENT_IS_READY;
PlIrqInstancePtr.IsStarted = 0;
t/*
t * Connect the PL IRQ to the interrupt subsystem so that interrupts
t * can occur
t */
t////////////////////////////////////////////
t u32tj=0;
t u32thigh_addr=0x0020ffff;
t u32 readvalue,valuer=0;
t// init_platform();
t// Xil_SetTlbAttributes(0xFFFF0000,0x14de2);
t for(j=0x0020ff00;j<high_addr;j++)
t ttt{
t tttif(valuer==65537)
t ttttvaluer=0;
t tttreadvalue=Xil_In16(XPAR_DDR_MEM_BASEADDR+(2*j));
t tttxil_printf("value_receive %d
",readvalue);
t tttvaluer++;
t }
t/////////////////////////////////////////////////////////////////////
tStatus = SetupIntrSystem(&IntcInstancePtr,
ttttt&PlIrqInstancePtr,
tttttPL_IRQ_ID);
tif (Status != XST_SUCCESS) {
ttreturn XST_FAILURE;
t}
while(1){
twhile(COMM_VAL == 0){};
tif(irq_count > 0) {
tprint("CPU1: Hello World With Interrupt CPU 1
r");
tirq_count = 0;
tsleep(2);tt//Delay so output can be seen
t} else {
ttsleep(5);
tprint("CPU1: Hello World CPU 1
r");
tsleep(5);
t}
tCOMM_VAL = 0;
}
t/*
t * Disable and disconnect the interrupt system
t */
tDisableIntrSystem(&IntcInstancePtr, PL_IRQ_ID);
return 0;
}
static int SetupIntrSystem(INTC *IntcInstancePtr,
ttXPlIrq *PeriphInstancePtr,
ttttu16 IntrId)
{
tint Status;
tXScuGic_Config *IntcConfig;
t/*
t * Initialize the interrupt controller driver so that it is ready to
t * use.
t */
tIntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
tif (NULL == IntcConfig) {
ttreturn XST_FAILURE;
t}
tStatus = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
tttttIntcConfig->CpuBaseAddress);
tif (Status != XST_SUCCESS) {
ttreturn XST_FAILURE;
t}
t/*
t * Connect the interrupt handler that will be called when an
t * interrupt occurs for the device.
t */
tStatus = XScuGic_Connect(IntcInstancePtr, IntrId,
tttt (Xil_ExceptionHandler)PlIntrHandler,
tttt PeriphInstancePtr);
tif (Status != XST_SUCCESS) {
ttreturn Status;
t}
t/*
t * Enable the interrupt for the PL device.
t */
tXScuGic_Enable(IntcInstancePtr, IntrId);
t/*
t * Initialize the exception table
t */
tXil_ExceptionInit();
t/*
t * Register the interrupt controller handler with the exception table
t */
tXil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
ttt (Xil_ExceptionHandler)INTC_HANDLER,
ttt IntcInstancePtr);
t/*
t * Enable non-critical exceptions
t */
tXil_ExceptionEnable();
treturn XST_SUCCESS;
}
static void PlIntrHandler(void *CallBackRef)
{
tXPlIrq *InstancePtr = (XPlIrq *)CallBackRef;
t/*
t * Clear the interrupt source
t */
tXil_Out32(InstancePtr->Config.BaseAddress, 0);
tirq_count = 1;
}
static void DisableIntrSystem(INTC *IntcInstancePtr, u16 IntrId)
{
t/*
t * Disconnect and disable the interrupt
t */
t/* Disconnect the interrupt */
tXScuGic_Disable(IntcInstancePtr, IntrId);
tXScuGic_Disconnect(IntcInstancePtr, IntrId);
}
RESULT:
cpu0
Hello World
High address=2162687
value at address is 0
value at address is 1
value at address is 2
value at address is 3
value at address is 4
value at address is 5
value at address is 6
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value at address is 247
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value at address is 249
value at address is 250
value at address is 251
value at address is 252
value at address is 253
value at address is 254
CPU0: writing startaddress for cpu1
CPU0: sending the SEV to wake up CPU1
CPU0: Hello World CPU 0
cpu1
CPU1: init_platform
value_receive 53411
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CPU1: Hello World CPU 1
CPU0: Hello World CPU 0
CPU1: Hello World CPU 1
CPU0: Hello World CPU 0
CPU1: Hello World CPU 1