Hi!
I'm playing around with a hashing algorithm.
Bitstream generation works well without timing issues.
When programming FPGA, no errors occur and the blue LED turns on to indicate that programming was succesful.
The design is connected to the PS using AXIlite. Writing and reading registers works out well for all but one of the regs: One of them is used to switch on the clock of the hasher by writing to it (using a BUFGCE).
As soon as I enable the clock (write to the corresponding reg), the blue LED turns off and the FPGA has to be reprogrammed. The serial connection used to observe results also closes, indicating that the whole system is reset.
What are possible reasons for this behaviour? To me (being a newbie to FPGA programming) it seems like a voltage drop or sth like that. This is supported by the fact that if I use half the number of (identical) hashing stages, the design works well - indicating that it should be working in principle.
As the design is quite big and using one single clock, I thought that a second BUFGCE for the second half of hashing stages could do the job, but this didn't work out also.
Any ideas?
Is this "reset" a normal behaviour at all or is it possible that some LUTs are broken?
I would have expected that a design which is implemented without timing errors should not suffer from "voltage drops", correct?
Thanks in advance!
