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Eth1 Gmii to Rgmii

Former Member

I am currently trying to implement an ethernet driven algorithm in the Zedboard. The board will interface with a GigE Vision Camera and I want to pull Ethernet packets directly into the Programmable Logic.
I understand that you need an external PHY that you provide ( I have one ordered). I am not fully understanding how to utilize the "GMII to RGMII v3.0" IP Core that Xilinx provides. I am not sure where that is sending the information.

It gives a gmii interface to the EMIO, but where do I access that data? I'm using Vivado 2014.2 and using the block design I can't see where the data will be accessed from the PS. When you switch the Eth1 peripheral to EMIO, it creates a GMII port in the processing system. This connects to the GMII port of the IP core.

Do you connect whatever customized IP you create to that same connection? Any information on how to correctly use this IP would be great.

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    Hello Jacob,

     

    Not sure exactly what you need to accomplish.

     

    If you use either of the Ethernet GigE Controllers (MAC) in the Zynq PS (Processor System), either Eth0 which is physically connected to the PHY on the ZedBoard, or Eth1 which you could connect to your external PHY via EMIO and the PL using the GMII to RGMII IP, you can have the packet data sent to an address you have implemented in your PL. You would probably use DMA to accomplish this.

     

    If you need to touch the raw data before it is processed by the Zynq GigE Controller you will need to implement some sort of Ethernet Controller (MAC) within the PL. There is a 'soft' Ethernet Controller IP that can be implemented in the PL or you may need to design your own, depending on your requirements.

     

    Perhaps you could provide a little more detail as to exactly what point you need to access the data and what you want to do with it.

     

    -Gary

  • 0 in reply to Former Member

    Thanks for the reply. I did a little more digging to see that if I wanted to use the PL without first running the data through the processor I would need to either develop the Ethernet controller or purchase the one that Xilinx provides (Tri-mode Ethernet MAC).

    At this point I will just access it after it is processed by the controller.

    Thanks for the help!

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