Hi,
I am trying to implement the Lab Exercise's from Intro to Zynq Tutorial.
I was able to complete the Labs 1-3.
I am stuck at Lab4 and unable to export XPS Design to SDK through PLANAHEAD since a long time.
In XPS, I have these warnings:
WARNING:EDK:4092 - IPNAME: axi_gpio, INSTANCE: axi_gpio_0 - Pre-Production version not verified on hardware for architecture 'zynq'
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 - Pre-Production version not verified on hardware for architecture 'zynq'
In PlanAhead I see:
[Edk 24-166] (generate_target): Failed to execute XPS script. Please check for any errors reported by the XPS application in the console: [C:/Users/USER/Documents/USER/ZED/ZYNC_LABS/project_3/project_3.srcs/sources_1/edk/module_1/__xps/pa/_module_1_synth.tcl]
I have followed the exact instructions provided in the lab tutorials to the boot. I have probably did it 20 times by now.
Any help with this will be greatly appreciated.
--------------------------------------------------------------------------------------------------
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--------------------------------------------------------------------------------------------------
In the PLAN_AHEAD TCL CONSOLE, I found some warning and info messages that might be of concern, can someone help me understand them:
Example:
axi_gpio_0 has been added to the project
ERROR:EDK:4125 - IPNAME: axi_gpio, INSTANCE: axi_gpio_0, PARAMETER: C_BASEADDR -
ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the
MHS.
ERROR:EDK:4125 - IPNAME: axi_gpio, INSTANCE: axi_gpio_0, PARAMETER: C_HIGHADDR -
ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the
MHS.
WARNING:EDK:2137 - Peripheral axi_gpio_0 is not accessible from any processor in
the system. Check Bus Interface connections and address parameters.
INFO:EDK - Successfully finished auto bus connection for IP instance: axi_gpio_0
Make instance axi_gpio_0 port GPIO_IO_O external with net as port name
Instance axi_gpio_0 port GPIO_IO_O connector undefined, using
*********************************************************************************************
--> You can find the full PLAN_AHEAD TCL CONSOLE DATA, PLAN_AHEAD MESSAGES Info, XPS module.mhs data below.
**********************************************************************************************
PLAN_AHEAD TCL CONSOLE:
__________________________
Assigned Driver generic 1.00.a for instance processing_system7_0
processing_system7_0 has been added to the project
INFO:EDK:3901 - please connect bus interface, set up port and generate address
manually
ZynqConfig: Terminated for gui mode
Writing filter settings....
Done writing filter settings to:
tC:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcss
ources_1edkmodule_1etcmodule_1.filters
Done writing Tab View settings to:
tC:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcss
ources_1edkmodule_1etcmodule_1.gui
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 28
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 28
Assigned Driver gpio 3.01.a for instance axi_gpio_0
axi_gpio_0 has been added to the project
ERROR:EDK:4125 - IPNAME: axi_gpio, INSTANCE: axi_gpio_0, PARAMETER: C_BASEADDR -
ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the
MHS.
ERROR:EDK:4125 - IPNAME: axi_gpio, INSTANCE: axi_gpio_0, PARAMETER: C_HIGHADDR -
ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the
MHS.
WARNING:EDK:2137 - Peripheral axi_gpio_0 is not accessible from any processor in
the system. Check Bus Interface connections and address parameters.
Assigned Driver generic 1.00.a for instance axi_interconnect_1
Address Map for Processor processing_system7_0
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) axi_gpio_0taxi_interconnect_1
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0
in design
INFO:EDK - Create new axi_interconnect IP instance axi_interconnect_1
INFO:EDK - Connect clock port M_AXI_GP0_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Connect bus interface S_AXI to axi_interconnect_1
INFO:EDK - Connect clock port S_AXI_ACLK to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in
processing_system7_0
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: axi_gpio_0
Make instance axi_gpio_0 port GPIO_IO_O external with net as port name
Instance axi_gpio_0 port GPIO_IO_O connector undefined, using
axi_gpio_0_GPIO_IO_O
ZynqConfig: Terminated for gui mode
Writing filter settings....
Done writing filter settings to:
tC:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcss
ources_1edkmodule_1etcmodule_1.filters
Done writing Tab View settings to:
tC:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcss
ources_1edkmodule_1etcmodule_1.gui
INFO: [Edk 24-127] XPS completed
create_xps: Time (s): elapsed = 00:09:22 . Memory (MB): peak = 458.551 ; gain = 7.973
make_wrapper -files [get_files C:/Users/USER/Documents/USER/ZED/ZYNC_LABS/project_3/project_3.srcs/sources_1/edk/module_1/module_1.xmp] -top -fileset [get_filesets sources_1] -import
INFO: [Edk 24-182] Generating top-level verilog wrapper for the XPS sub-design source 'module_1'...
Xilinx Platform Studio
Xilinx EDK 14.6 Build EDK_P.68d
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
XPS% Evaluating file
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcsso
urces_1edkmodule_1__xpspa_module_1_top.tcl
WARNING:EDK - IPNAME: processing_system7, INSTANCE: processing_system7_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 30
WARNING:EDK - IPNAME: axi_gpio, INSTANCE: axi_gpio_0 - Pre-Production version
not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 118
WARNING:EDK - IPNAME: processing_system7, INSTANCE: processing_system7_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 30
WARNING:EDK - IPNAME: axi_gpio, INSTANCE: axi_gpio_0 - Pre-Production version
not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 118
Overriding IP level properties ...
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 300
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 304
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 308
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 312
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 319
INFO:EDK - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_BASEFAMILY value to zynq -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresaxi_interconnect_v1_
06_adataaxi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK - Frequency for Top-Level Input Clock 'processing_system7_0_PS_CLK_pin'
is not specified. Clock DRCs will not be performed for IPs connected to that
clock port, unless they are connected through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is
0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable
Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a
master on processing_system7 AXI slave interfaces, please use the top half of
the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For
all other master, any subset of the DDR address can be used. See Xilinx
Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) axi_gpio_0taxi_interconnect_1
Checking platform address map ...
Overriding IP level properties ...
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 300
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 304
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 308
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 312
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 319
INFO:EDK - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_BASEFAMILY value to zynq -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresaxi_interconnect_v1_
06_adataaxi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK - Frequency for Top-Level Input Clock 'processing_system7_0_PS_CLK_pin'
is not specified. Clock DRCs will not be performed for IPs connected to that
clock port, unless they are connected through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is
0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable
Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a
master on processing_system7 AXI slave interfaces, please use the top half of
the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For
all other master, any subset of the DDR address can be used. See Xilinx
Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) axi_gpio_0taxi_interconnect_1
Checking platform address map ...
Command Line: platgen -p xc7z020clg484-1 -lang verilog -intstyle pa -stubgen
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcsso
urces_1edkmodule_1module_1.mhs
WARNING:EDK - INFO:Security:71 - If a license for part 'xc7z020' is available,
it will be possible to use 'XPS_TDP' instead of 'XPS'.
WARNING:Security:42 - Your software subscription period has lapsed. Your
current version of Xilinx tools will continue to function, but you no longer
qualify for Xilinx software updates or new releases.
Parse
C:/Users/USER/Documents/USER/ZED/ZYNC_LABS/project_3/project_3.srcs/so
urces_1/edk/module_1/module_1.mhs ...
Create merged mhs ...
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 30
WARNING:EDK:4092 - IPNAME: axi_gpio, INSTANCE: axi_gpio_0 - Pre-Production
version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 118
Overriding IP level properties ...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 300
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 304
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 308
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 312
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 319
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_BASEFAMILY value to zynq -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresaxi_interconnect_v1_
06_adataaxi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK:1432 - Frequency for Top-Level Input Clock
'processing_system7_0_PS_CLK_pin' is not specified. Clock DRCs will not be
performed for IPs connected to that clock port, unless they are connected
through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is
0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable
Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a
master on processing_system7 AXI slave interfaces, please use the top half of
the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For
all other master, any subset of the DDR address can be used. See Xilinx
Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) axi_gpio_0taxi_interconnect_1
Checking platform address map ...
Modify defaults ...
Creating stub ...
Elaborating instances ...
Inserting wrapper level ...
Writing (stub) BMM ...
Writing top-level HDL ...
Total run time: 6.00 seconds
Overriding IP level properties ...
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 300
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 304
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 308
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 312
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 319
INFO:EDK - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_BASEFAMILY value to zynq -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresaxi_interconnect_v1_
06_adataaxi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK - Frequency for Top-Level Input Clock 'processing_system7_0_PS_CLK_pin'
is not specified. Clock DRCs will not be performed for IPs connected to that
clock port, unless they are connected through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is
0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable
Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a
master on processing_system7 AXI slave interfaces, please use the top half of
the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For
all other master, any subset of the DDR address can be used. See Xilinx
Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) axi_gpio_0taxi_interconnect_1
Checking platform address map ...
INFO: [Edk 24-126] Wrapper generated:C:/Users/USER/Documents/USER/ZED/ZYNC_LABS/project_3/project_3.srcs/sources_1/edk/module_1/module_1_stub.v
make_wrapper: Time (s): elapsed = 00:00:20 . Memory (MB): peak = 464.195 ; gain = 5.223
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
add_files -norecurse -scan_for_includes C:/Users/USER/Documents/USER/ZED/Zynq_Intro_Online_v01/Zynq_Intro/support_documents/PWM_Controller.v
import_files -norecurse C:/Users/USER/Documents/USER/ZED/Zynq_Intro_Online_v01/Zynq_Intro/support_documents/PWM_Controller.v
update_compile_order -fileset sources_1
add_files -fileset constrs_1 -norecurse C:/Users/USER/Documents/USER/ZED/Zynq_Intro_Online_v01/Zynq_Intro/support_documents/zedboard_master_UCF_RevC_v3.ucf
import_files -fileset constrs_1 C:/Users/USER/Documents/USER/ZED/Zynq_Intro_Online_v01/Zynq_Intro/support_documents/zedboard_master_UCF_RevC_v3.ucf
update_compile_order -fileset sources_1
reset_run impl_1
launch_runs synth_1
INFO: [Edk 24-181] Generating synthesized netlists for the XPS sub-design source 'module_1'...
Xilinx Platform Studio
Xilinx EDK 14.6 Build EDK_P.68d
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
XPS% Evaluating file
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcsso
urces_1edkmodule_1__xpspa_module_1_synth.tcl
WARNING:EDK - IPNAME: processing_system7, INSTANCE: processing_system7_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 30
WARNING:EDK - IPNAME: axi_gpio, INSTANCE: axi_gpio_0 - Pre-Production version
not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 118
WARNING:EDK - IPNAME: processing_system7, INSTANCE: processing_system7_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 30
WARNING:EDK - IPNAME: axi_gpio, INSTANCE: axi_gpio_0 - Pre-Production version
not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 118
Overriding IP level properties ...
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 300
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 304
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 308
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 312
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 319
INFO:EDK - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_BASEFAMILY value to zynq -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresaxi_interconnect_v1_
06_adataaxi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK - Frequency for Top-Level Input Clock 'processing_system7_0_PS_CLK_pin'
is not specified. Clock DRCs will not be performed for IPs connected to that
clock port, unless they are connected through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is
0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable
Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a
master on processing_system7 AXI slave interfaces, please use the top half of
the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For
all other master, any subset of the DDR address can be used. See Xilinx
Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) axi_gpio_0taxi_interconnect_1
Checking platform address map ...
Overriding IP level properties ...
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 300
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 304
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 308
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 312
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 319
INFO:EDK - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_BASEFAMILY value to zynq -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresaxi_interconnect_v1_
06_adataaxi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK - Frequency for Top-Level Input Clock 'processing_system7_0_PS_CLK_pin'
is not specified. Clock DRCs will not be performed for IPs connected to that
clock port, unless they are connected through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is
0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable
Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a
master on processing_system7 AXI slave interfaces, please use the top half of
the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For
all other master, any subset of the DDR address can be used. See Xilinx
Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) axi_gpio_0taxi_interconnect_1
Checking platform address map ...
"****************************************************"
"Creating system netlist for hardware specification.."
"****************************************************"
platgen -p xc7z020clg484-1 -lang verilog -intstyle pa -toplevel no -ti module_1_i -msg __xps/ise/xmsgprops.lst module_1.mhs
Command Line: platgen -p xc7z020clg484-1 -lang verilog -intstyle pa -toplevel no
-ti module_1_i -msg __xps/ise/xmsgprops.lst module_1.mhs
WARNING:EDK - INFO:Security:71 - If a license for part 'xc7z020' is available,
it will be possible to use 'XPS_TDP' instead of 'XPS'.
WARNING:Security:42 - Your software subscription period has lapsed. Your
current version of Xilinx tools will continue to function, but you no longer
qualify for Xilinx software updates or new releases.
Parse
C:/Users/USER/Documents/USER/ZED/ZYNC_LABS/project_3/project_3.srcs/so
urces_1/edk/module_1/module_1.mhs ...
Read MPD definitions ...
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 30
WARNING:EDK:4092 - IPNAME: axi_gpio, INSTANCE: axi_gpio_0 - Pre-Production
version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 118
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 30
WARNING:EDK:4092 - IPNAME: axi_gpio, INSTANCE: axi_gpio_0 - Pre-Production
version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 118
Overriding IP level properties ...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 300
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 304
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 308
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 312
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 319
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_BASEFAMILY value to zynq -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresaxi_interconnect_v1_
06_adataaxi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK:1432 - Frequency for Top-Level Input Clock
'processing_system7_0_PS_CLK_pin' is not specified. Clock DRCs will not be
performed for IPs connected to that clock port, unless they are connected
through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is
0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable
Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a
master on processing_system7 AXI slave interfaces, please use the top half of
the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For
all other master, any subset of the DDR address can be used. See Xilinx
Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) axi_gpio_0taxi_interconnect_1
Checking platform address map ...
Checking platform configuration ...
IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 1
slave(s)
Checking port drivers...
ERROR:EDK:4074 - INSTANCE: axi_gpio_0, PORT: GPIO_IO, CONNECTOR:
axi_gpio_0_GPIO_IO - No driver found -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 125
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/module_1_processing_system7_0_wrapper.ngc] Error 2
ERROR:EDK -
Error while running "make -f module_1.make netlist".
ERROR: [Edk 24-166] (generate_target): Failed to execute XPS script. Please check for any errors reported by the XPS application in the console: [C:/Users/USER/Documents/USER/ZED/ZYNC_LABS/project_3/project_3.srcs/sources_1/edk/module_1/__xps/pa/_module_1_synth.tcl]
--------------------------------------------------------------------------------------------------
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--------------------------------------------------------------------------------------------------
PLAN_AHEAD MESSAGES INFO:
_________________________
PlanAhead Commands
create_xps module_1
make_wrapper -files [get_files C:/Users/USER/Documents/USER/ZED/ZYNC_LABS/project_3/project_3.srcs/sources_1/edk/module_1/module_1.xmp] -top -fileset [get_filesets sources_1] -import
launch_runs synth_1
[Edk 24-181] Generating synthesized netlists for the XPS sub-design source 'module_1'...
Xilinx Platform Studio
Xilinx EDK 14.6 Build EDK_P.68d
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
XPS% Evaluating file
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcsso
urces_1edkmodule_1__xpspa_module_1_synth.tcl
WARNING:EDK - IPNAME: processing_system7, INSTANCE: processing_system7_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 30
WARNING:EDK - IPNAME: axi_gpio, INSTANCE: axi_gpio_0 - Pre-Production version
not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 118
WARNING:EDK - IPNAME: processing_system7, INSTANCE: processing_system7_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 30
WARNING:EDK - IPNAME: axi_gpio, INSTANCE: axi_gpio_0 - Pre-Production version
not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABS
project_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 118
Overriding IP level properties ...
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 300
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 304
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 308
INFO:EDK - IPNAME: processing_system7, INSTANCE:processin
g_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 312
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 319
INFO:EDK - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_BASEFAMILY value to zynq -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresaxi_interconnect_v1_
06_adataaxi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK - Frequency for Top-Level Input Clock 'processing_system7_0_PS_CLK_pin'
is not specified. Clock DRCs will not be performed for IPs connected to that
clock port, unless they are connected through the clock generator
IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is
0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable
Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a
master on processing_system7 AXI slave interfaces, please use the top half of
the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For
all other master, any subset of the DDR address can be used. See Xilinx
Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) axi_gpio_0taxi_interconnect_1
Checking platform address map ...
Overriding IP level properties ...
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 300
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 304
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 308
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x
1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 312
INFO:EDK - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl is
overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 319
INFO:EDK - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_BASEFAMILY value to zynq -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresaxi_interconnect_v1_
06_adataaxi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK - Frequency for Top-Level Input Clock 'processing_system7_0_PS_CLK_pin'
is not specified. Clock DRCs will not be performed for IPs connected to that
clock port, unless they are connected through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedu
res for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is
0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable
Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a
master on processing_system7 AXI slave interfaces, please use the top half of
the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For
all other master, any subset of the DDR address can be used. See Xilinx
Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) axi_gpio_0taxi_interconnect_1
Checking platform address map ...
"****************************************************"
"Creating system netlist for hardware specification.."
"****************************************************"
platgen -p xc7z020clg484-1 -lang verilog -intstyle pa -toplevel no -ti module_1_i -msg __xps/ise/xmsgprops.lst module_1.mhs
Command Line: platgen -p xc7z020clg484-1 -lang verilog -intstyle pa -toplevel no
-ti module_1_i -msg __xps/ise/xmsgprops.lst module_1.mhs
WARNING:EDK - INFO:Security:71 - If a license for part 'xc7z020' is available,
it will be possible to use 'XPS_TDP' instead of 'XPS'.
WARNING:Security:42 - Your software subscription period has lapsed. Your
current version of Xilinx tools will continue to function, but you no longer
qualify for Xilinx software updates or new releases.
Parse
C:/Users/USER/Documents/USER/ZED/ZYNC_LABS/project_3/project_3.srcs/so
urces_1/edk/module_1/module_1.mhs ...
Read MPD definitions ...
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 30
WARNING:EDK:4092 - IPNAME: axi_gpio, INSTANCE: axi_gpio_0 - Pre-Production
version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 118
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 30
WARNING:EDK:4092 - IPNAME: axi_gpio, INSTANCE: axi_gpio_0 - Pre-Production
version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 118
Overriding IP level properties ...
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 300
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to
0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 304
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 308
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 312
INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl
is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 1 -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresprocessing_system7_v
4_03_adataprocessing_system7_v2_1_0.mpd line 319
INFO:EDK:4130
- IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is
overriding PARAMETER C_BASEFAMILY value to zynq -
C:Xilinx14.6ISE_DSEDKhwXilinxProcessorIPLibpcoresaxi_interconnect_v1_
06_adataaxi_interconnect_v2_1_0.mpd line 81
Computing clock values...
INFO:EDK:1432 - Frequency for Top-Level Input Clock
'processing_system7_0_PS_CLK_pin' is not specified. Clock DRCs will not be
performed for IPs connected to that clock port, unless they are connected
through the clock generator IP.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
INFO:EDK - INFO: DDR Base and High address in current configuration is
0x00000000 and 0x1FFFFFFF respectively.
INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable
Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a
master on processing_system7 AXI slave interfaces, please use the top half of
the address range (Base Ad
dress = 0x10000000; High Address = 0x1FFFFFFF). For
all other master, any subset of the DDR address can be used. See Xilinx
Answer 47167 for more information.
Address Map for Processor processing_system7_0
(0x41200000-0x4120ffff) axi_gpio_0taxi_interconnect_1
Checking platform address map ...
Checking platform configuration ...
IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 1
slave(s)
Checking port drivers...
ERROR:EDK:4074 - INSTANCE: axi_gpio_0, PORT: GPIO_IO, CONNECTOR:
axi_gpio_0_GPIO_IO - No driver found -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 125
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/module_1_processing_system7_0_wrapper.ngc] Error 2
ERROR:EDK -
Error while running "make -f module_1.make netlist".
[Edk 24-166] (generate_target): Failed to execute XPS script. Please check for any errors reported by the XPS application in the console: [C:/Users/USER/Documents/USER/ZED/ZYNC_LABS/project_3/project_3.srcs/sources_1/edk/module_1/__xps/pa/_module_1_synth.tcl]
[Edk 24-184] Launching XPS (Xilinx Platform Studio) for configuring XPS sub-design source 'module_1'...
Xilinx Platform Studio
Xilinx EDK 14.6 Build EDK_P.68d
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Launching XPS GUI...
INFO:EDK - Simulation, Implementation and Device configuration flows are
disabled in XPS when launched from PlanAhead. All these features are
available in PlanAhead.
MainWindow
INFO:EDK - WARNING:Security:42 - Your software subscription period has lapsed.
Your current version of Xilinx tools will continue to function, but you no
longer qualify for Xilinx software updates or new releases.
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 30
WARNING:EDK:4092 - IPNAME: axi_gpio, INSTANCE: axi_gpio_0 - Pre-Production
version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 118
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -
Pre-Production version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocumentsUSERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 30
WARNING:EDK:4092 - IPNAME: axi_gpio, INSTANCE: axi_gpio_0 - Pre-Production
version not verified on hardware for architecture 'zynq' -
C:UsersUSERDocuments
USERZEDZYNC_LABSproject_3project_3.srcs
sources_1edkmodule_1module_1.mhs line 118
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XPS Module .mhs data: ( Warnings are generated for line 130 and line 118, I marked both lines)
______________________________________________________________________________________________
PARAMETER VERSION = 2.1.0
PORT processing_system7_0_MIO = processing_system7_0_MIO, DIR = IO, VEC = [53:0]
PORT processing_system7_0_PS_SRSTB_pin = processing_system7_0_PS_SRSTB, DIR = I
PORT processing_system7_0_PS_CLK_pin = processing_system7_0_PS_CLK, DIR = I, SIGIS = CLK
PORT processing_system7_0_PS_PORB_pin = processing_system7_0_PS_PORB, DIR = I
PORT processing_system7_0_DDR_Clk = processing_system7_0_DDR_Clk, DIR = IO, SIGIS = CLK
PORT processing_system7_0_DDR_Clk_n = processing_system7_0_DDR_Clk_n, DIR = IO, SIGIS = CLK
PORT processing_system7_0_DDR_CKE = processing_system7_0_DDR_CKE, DIR = IO
PORT processing_system7_0_DDR_CS_n = processing_system7_0_DDR_CS_n, DIR = IO
PORT processing_system7_0_DDR_RAS_n = processing_system7_0_DDR_RAS_n, DIR = IO
PORT processing_system7_0_DDR_CAS_n = processing_system7_0_DDR_CAS_n, DIR = IO
PORT processing_system7_0_DDR_WEB_pin = processing_system7_0_DDR_WEB, DIR = O
PORT processing_system7_0_DDR_BankAddr = processing_system7_0_DDR_BankAddr, DIR = IO, VEC = [2:0]
PORT processing_system7_0_DDR_Addr = processing_system7_0_DDR_Addr, DIR = IO, VEC = [14:0]
PORT processing_system7_0_DDR_ODT = processing_system7_0_DDR_ODT, DIR = IO
PORT processing_system7_0_DDR_DRSTB = processing_system7_0_DDR_DRSTB, DIR = IO, SIGIS = RST
PORT processing_system7_0_DDR_DQ = processing_system7_0_DDR_DQ, DIR = IO, VEC = [31:0]
PORT processing_system7_0_DDR_DM = processing_system7_0_DDR_DM, DIR = IO, VEC = [3:0]
PORT processing_system7_0_DDR_DQS = processing_system7_0_DDR_DQS, DIR = IO, VEC = [3:0]
PORT processing_system7_0_DDR_DQS_n = processing_system7_0_DDR_DQS_n, DIR = IO, VEC = [3:0]
PORT processing_system7_0_DDR_VRN = processing_system7_0_DDR_VRN, DIR = IO
PORT processing_system7_0_DDR_VRP = processing_system7_0_DDR_VRP, DIR = IO
PORT axi_gpio_0_GPIO_IO_O_pin = axi_gpio_0_GPIO_IO_O, DIR = O, VEC = [31:0]
PORT processing_system7_0_FCLK_CLK0_pin = processing_system7_0_FCLK_CLK0, DIR = O, SIGIS = CLK, CLK_FREQ = 100000000
BEGIN processing_system7
PARAMETER INSTANCE = processing_system7_0
PARAMETER HW_VER = 4.03.a
PARAMETER C_DDR_RAM_HIGHADDR = 0x1FFFFFFF
PARAMETER C_EN_EMIO_CAN0 = 0
PARAMETER C_EN_EMIO_CAN1 = 0
PARAMETER C_EN_EMIO_ENET0 = 0
PARAMETER C_EN_EMIO_ENET1 = 0
PARAMETER C_EN_EMIO_I2C0 = 0
PARAMETER C_EN_EMIO_I2C1 = 0
PARAMETER C_EN_EMIO_PJTAG = 0
PARAMETER C_EN_EMIO_SDIO0 = 0
PARAMETER C_EN_EMIO_CD_SDIO0 = 0
PARAMETER C_EN_EMIO_WP_SDIO0 = 0
PARAMETER C_EN_EMIO_SDIO1 = 0
PARAMETER C_EN_EMIO_CD_SDIO1 = 0
PARAMETER C_EN_EMIO_WP_SDIO1 = 0
PARAMETER C_EN_EMIO_SPI0 = 0
PARAMETER C_EN_EMIO_SPI1 = 0
PARAMETER C_EN_EMIO_SRAM_INT = 0
PARAMETER C_EN_EMIO_TRACE = 0
PARAMETER C_EN_EMIO_TTC0 = 1
PARAMETER C_EN_EMIO_TTC1 = 0
PARAMETER C_EN_EMIO_UART0 = 0
PARAMETER C_EN_EMIO_UART1 = 0
PARAMETER C_EN_EMIO_MODEM_UART0 = 0
PARAMETER C_EN_EMIO_MODEM_UART1 = 0
PARAMETER C_EN_EMIO_WDT = 0
PARAMETER C_EN_EMIO_GPIO = 0
PARAMETER C_EMIO_GPIO_WIDTH = 64
PARAMETER C_EN_QSPI = 1
PARAMETER C_EN_SMC = 0
PARAMETER C_EN_CAN0 = 0
PARAMETER C_EN_CAN1 = 0
PARAMETER C_EN_ENET0 = 1
PARAMETER C_EN_ENET1 = 0
PARAMETER C_EN_I2C0 = 0
PARAMETER C_EN_I2C1 = 0
PARAMETER C_EN_PJTAG = 0
PARAMETER C_EN_SDIO0 = 1
PARAMETER C_EN_SDIO1 = 0
PARAMETER C_EN_SPI0 = 0
PARAMETER C_EN_SPI1 = 0
PARAMETER C_EN_TRACE = 0
PARAMETER C_EN_TTC0 = 1
PARAMETER C_EN_TTC1 = 0
PARAMETER C_EN_UART0 = 0
PARAMETER C_EN_UART1 = 1
PARAMETER C_EN_MODEM_UART0 = 0
PARAMETER C_EN_MODEM_UART1 = 0
PARAMETER C_EN_USB0 = 1
PARAMETER C_EN_USB1 = 0
PARAMETER C_EN_WDT = 0
PARAMETER C_EN_DDR = 1
PARAMETER C_EN_GPIO = 1
PARAMETER C_FCLK_CLK0_FREQ = 100000000
PARAMETER C_FCLK_CLK1_FREQ = 142857132
PARAMETER C_FCLK_CLK2_FREQ = 50000000
PARAMETER C_FCLK_CLK3_FREQ = 50000000
PARAMETER C_USE_CR_FABRIC = 1
PARAMETER C_USE_M_AXI_GP0 = 1
BUS_INTERFACE M_AXI_GP0 = axi_interconnect_1
PORT MIO = processing_system7_0_MIO
PORT PS_SRSTB = processing_system7_0_PS_SRSTB
PORT PS_CLK = processing_system7_0_PS_CLK
PORT PS_PORB = processing_system7_0_PS_PORB
PORT DDR_Clk = processing_system7_0_DDR_Clk
PORT DDR_Clk_n = processing_system7_0_DDR_Clk_n
PORT DDR_CKE = processing_system7_0_DDR_CKE
PORT DDR_CS_n = processing_system7_0_DDR_CS_n
PORT DDR_RAS_n = processing_system7_0_DDR_RAS_n
PORT DDR_CAS_n = processing_system7_0_DDR_CAS_n
PORT DDR_WEB = processing_system7_0_DDR_WEB
PORT DDR_BankAddr = processing_system7_0_DDR_BankAddr
PORT DDR_Addr = processing_system7_0_DDR_Addr
PORT DDR_ODT = processing_system7_0_DDR_ODT
PORT DDR_DRSTB = processing_system7_0_DDR_DRSTB
PORT DDR_DQ = processing_system7_0_DDR_DQ
PORT DDR_DM = processing_system7_0_DDR_DM
PORT DDR_DQS = processing_system7_0_DDR_DQS
PORT DDR_DQS_n = processing_system7_0_DDR_DQS_n
PORT DDR_VRN = processing_system7_0_DDR_VRN
PORT DDR_VRP = processing_system7_0_DDR_VRP
PORT FCLK_CLK0 = processing_system7_0_FCLK_CLK0
PORT FCLK_RESET0_N = processing_system7_0_FCLK_RESET0_N
PORT M_AXI_GP0_ACLK = processing_system7_0_FCLK_CLK0
END
--> Line 118: BEGIN axi_gpio
PARAMETER INSTANCE = axi_gpio_0
PARAMETER HW_VER = 1.01.b
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120ffff
BUS_INTERFACE S_AXI = axi_interconnect_1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
PORT GPIO_IO = axi_gpio_0_GPIO_IO
PORT GPIO_IO_O = axi_gpio_0_GPIO_IO_O
END
--> Line 130: BEGIN axi_interconnect
PARAMETER INSTANCE = axi_interconnect_1
PARAMETER HW_VER = 1.06.a
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0
PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
END
Thank you very much for your time and consideration for reaching the end of the post.
Any help from AVNET and Zedboard Users will immensely help me proceed to the next stage and learn more about using Xilinx Tools and the Zedboard.
-
VK.
